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author | Jim Grosbach <grosbach@apple.com> | 2011-08-19 16:52:32 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-08-19 16:52:32 +0000 |
commit | c6d7c653c9d4a54e62ac8da92518caa96d0a349c (patch) | |
tree | 13ad0676f7169e475da91d5d8794cdfa00c90622 | |
parent | 67a9b1fcc797e923ad610e741e5ef3ea6b7aabf2 (diff) |
Add explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138042 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 199691f6c3..a6e0ed737b 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -125,6 +125,11 @@ def t_addrmode_rr : Operand<i32>, // t_addrmode_rrs := reg + reg // +// We use separate scaled versions because the Select* functions need +// to explicitly check for a matching constant and return false here so that +// the reg+imm forms will match instead. This is a horrible way to do that, +// as it forces tight coupling between the methods, but it's how selectiondag +// currently works. def t_addrmode_rrs1 : Operand<i32>, ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { let EncoderMethod = "getThumbAddrModeRegRegOpValue"; |