diff options
author | Benjamin Kramer <benny.kra@googlemail.com> | 2010-11-25 16:42:51 +0000 |
---|---|---|
committer | Benjamin Kramer <benny.kra@googlemail.com> | 2010-11-25 16:42:51 +0000 |
commit | c62feda741f9d5811b625967c40f1847fb2040e7 (patch) | |
tree | c192a039e5f18c798113836dd6a8c597cc5acc65 | |
parent | 6b8e4357ecb77a97e08557896f06fd45550c9e46 (diff) |
Namespacify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120146 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/RegAllocBasic.cpp | 4 | ||||
-rw-r--r-- | lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp index 76c243c743..6af5e6c889 100644 --- a/lib/CodeGen/RegAllocBasic.cpp +++ b/lib/CodeGen/RegAllocBasic.cpp @@ -56,6 +56,8 @@ static cl::opt<bool> VerifyRegAlloc("verify-regalloc", cl::desc("Verify live intervals before renaming")); +namespace { + class PhysicalRegisterDescription : public AbstractRegisterDescription { const TargetRegisterInfo *tri_; public: @@ -63,8 +65,6 @@ public: virtual const char *getName(unsigned reg) const { return tri_->getName(reg); } }; -namespace { - /// RABasic provides a minimal implementation of the basic register allocation /// algorithm. It prioritizes live virtual registers by spill weight and spills /// whenever a register is unavailable. This is not practical in production but diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp index c8037b3b6a..c8db0c4047 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -222,7 +222,7 @@ void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo, /// stripRegisterPrefix - This method strips the character prefix from a /// register name so that only the number is left. Used by for linux asm. -const char *stripRegisterPrefix(const char *RegName) { +static const char *stripRegisterPrefix(const char *RegName) { switch (RegName[0]) { case 'r': case 'f': |