Start eliminating temporary vectors used to create DAG nodes. Instead, pass

in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29566 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 262 insertions, 360 deletions

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 6ba236c0ff..204b2eb856 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -145,12 +145,8 @@ public:
     std::vector<MVT::ValueType> VTs;
     VTs.push_back(MVT::Other);
     VTs.push_back(MVT::Flag);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(Chain);
-    Ops.push_back(getRegister(Reg, N.getValueType()));
-    Ops.push_back(N);
-    if (Flag.Val) Ops.push_back(Flag);
-    return getNode(ISD::CopyToReg, VTs, Ops);
+    SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
+    return getNode(ISD::CopyToReg, VTs, Ops, Flag.Val ? 4 : 3);
   }
 
   // Similar to last getCopyToReg() except parameter Reg is a SDOperand
@@ -159,12 +155,8 @@ public:
     std::vector<MVT::ValueType> VTs;
     VTs.push_back(MVT::Other);
     VTs.push_back(MVT::Flag);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(Chain);
-    Ops.push_back(Reg);
-    Ops.push_back(N);
-    if (Flag.Val) Ops.push_back(Flag);
-    return getNode(ISD::CopyToReg, VTs, Ops);
+    SDOperand Ops[] = { Chain, Reg, N, Flag };
+    return getNode(ISD::CopyToReg, VTs, Ops, Flag.Val ? 4 : 3);
   }
   
   SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
@@ -218,14 +210,17 @@ public:
                     SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
                     SDOperand N5);
   SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
-                    std::vector<SDOperand> &Children);
-  SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
-                    std::vector<SDOperand> &Ops);
-
-  SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
                     const SDOperand *Ops, unsigned NumOps);
+  SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
+                    const std::vector<SDOperand> &Ops) {
+    return getNode(Opcode, VT, &Ops[0], Ops.size());
+  }
   SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
                     const SDOperand *Ops, unsigned NumOps);
+  SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
+                    const std::vector<SDOperand> &Ops) {
+    return getNode(Opcode, ResultTys, &Ops[0], Ops.size());
+  }
   
   
   /// getSetCC - Helper function to make it easier to build SetCC's if you just
@@ -351,7 +346,7 @@ public:
                         SDOperand Op4, SDOperand Op5, SDOperand Op6,
                         SDOperand Op7, SDOperand Op8);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
-                        std::vector<SDOperand> &Ops);
+                        const SDOperand *Ops, unsigned NumOps);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                         MVT::ValueType VT2, SDOperand Op1);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
@@ -391,7 +386,8 @@ public:
                         SDOperand Op3, SDOperand Op4, SDOperand Op5,
                         SDOperand Op6, SDOperand Op7);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, 
-                        MVT::ValueType VT2, std::vector<SDOperand> &Ops);
+                        MVT::ValueType VT2,
+                        const SDOperand *Ops, unsigned NumOps);
   
   /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
   /// This can cause recursive merging of nodes in the DAG.  Use the first
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a767cd971e..aa325b3ba4 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -510,7 +510,7 @@ SDOperand DAGCombiner::visit(SDNode *N) {
 }
 
 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
-  std::vector<SDOperand> Ops;
+  SmallVector<SDOperand, 8> Ops;
   bool Changed = false;
 
   // If the token factor has two operands and one is the entry token, replace
@@ -539,7 +539,7 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
     }
   }
   if (Changed)
-    return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
+    return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
   return SDOperand();
 }
 
@@ -1284,7 +1284,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
       // Produce a vector of zeros.
       SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
       std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
-      return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+      return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
     }
   }
   
@@ -1953,14 +1953,14 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
   // If this is a conversion of N elements of one type to N elements of another
   // type, convert each element.  This handles FP<->INT cases.
   if (SrcBitSize == DstBitSize) {
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
       AddToWorkList(Ops.back().Val);
     }
     Ops.push_back(*(BV->op_end()-2)); // Add num elements.
     Ops.push_back(DAG.getValueType(DstEltVT));
-    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
   }
   
   // Otherwise, we're growing or shrinking the elements.  To avoid having to
@@ -1992,7 +1992,7 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
   if (SrcBitSize < DstBitSize) {
     unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
     
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
          i += NumInputsPerOutput) {
       bool isLE = TLI.isLittleEndian();
@@ -2016,13 +2016,13 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
 
     Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
     Ops.push_back(DAG.getValueType(DstEltVT));            // Add element size.
-    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
   }
   
   // Finally, this must be the case where we are shrinking elements: each input
   // turns into multiple outputs.
   unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
-  std::vector<SDOperand> Ops;
+  SmallVector<SDOperand, 8> Ops;
   for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
     if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
       for (unsigned j = 0; j != NumOutputsPerInput; ++j)
@@ -2043,7 +2043,7 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
   }
   Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
   Ops.push_back(DAG.getValueType(DstEltVT));            // Add element size.
-  return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+  return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
 }
 
 
@@ -2448,10 +2448,11 @@ SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
   // vector with the inserted element.
   if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
-    std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
     if (Elt < Ops.size())
       Ops[Elt] = InVal;
-    return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
+    return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
+                       &Ops[0], Ops.size());
   }
   
   return SDOperand();
@@ -2468,10 +2469,11 @@ SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
   // vector with the inserted element.
   if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
-    std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
     if (Elt < Ops.size()-2)
       Ops[Elt] = InVal;
-    return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
+    return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
+                       &Ops[0], Ops.size());
   }
   
   return SDOperand();
@@ -2524,7 +2526,7 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
   
   // If everything is good, we can make a shuffle operation.
   if (VecIn1.Val) {
-    std::vector<SDOperand> BuildVecIndices;
+    SmallVector<SDOperand, 8> BuildVecIndices;
     for (unsigned i = 0; i != NumInScalars; ++i) {
       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
         BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
@@ -2549,10 +2551,10 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
     BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
     
     // Return the new VVECTOR_SHUFFLE node.
-    std::vector<SDOperand> Ops;
-    Ops.push_back(VecIn1);
+    SDOperand Ops[5];
+    Ops[0] = VecIn1;
     if (VecIn2.Val) {
-      Ops.push_back(VecIn2);
+      Ops[1] = VecIn2;
     } else {
        // Use an undef vbuild_vector as input for the second operand.
       std::vector<SDOperand> UnOps(NumInScalars,
@@ -2560,13 +2562,15 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
                                            cast<VTSDNode>(EltType)->getVT()));
       UnOps.push_back(NumElts);
       UnOps.push_back(EltType);
-      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
-      AddToWorkList(Ops.back().Val);
+      Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                           &UnOps[0], UnOps.size());
+      AddToWorkList(Ops[1].Val);
     }
-    Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
-    Ops.push_back(NumElts);
-    Ops.push_back(EltType);
-    return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+    Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                         &BuildVecIndices[0], BuildVecIndices.size());
+    Ops[3] = NumElts;
+    Ops[4] = EltType;
+    return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
   }
   
   return SDOperand();
@@ -2668,7 +2672,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
       return DAG.getNode(ISD::UNDEF, N->getValueType(0));
     // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
     // first operand.
-    std::vector<SDOperand> MappedOps;
+    SmallVector<SDOperand, 8> MappedOps;
     for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
       if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
           cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -2680,7 +2684,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
       }
     }
     ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
-                           MappedOps);
+                           &MappedOps[0], MappedOps.size());
     AddToWorkList(ShufMask.Val);
     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
                        N0, 
@@ -2785,7 +2789,7 @@ SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
   if (isUnary || N0 == N1) {
     // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
     // first operand.
-    std::vector<SDOperand> MappedOps;
+    SmallVector<SDOperand, 8> MappedOps;
     for (unsigned i = 0; i != NumElts; ++i) {
       if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
           cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -2801,7 +2805,7 @@ SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
     MappedOps.push_back(ShufMask.getOperand(NumElts+1));
 
     ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
-                           MappedOps);
+                           &MappedOps[0], MappedOps.size());
     AddToWorkList(ShufMask.Val);
     
     // Build the undef vector.
@@ -2810,7 +2814,8 @@ SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
       MappedOps[i] = UDVal;
     MappedOps[NumElts  ] = *(N0.Val->op_end()-2);
     MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
-    UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
+    UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                        &MappedOps[0], MappedOps.size());
     
     return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 
                        N0, UDVal, ShufMask,
@@ -2863,13 +2868,16 @@ SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
       std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
       ZeroOps.push_back(NumEltsNode);
       ZeroOps.push_back(EVTNode);
-      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
+      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                                &ZeroOps[0], ZeroOps.size()));
       IdxOps.push_back(NumEltsNode);
       IdxOps.push_back(EVTNode);
-      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
+      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                                &IdxOps[0], IdxOps.size()));
       Ops.push_back(NumEltsNode);
       Ops.push_back(EVTNode);
-      SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+      SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
+                                     &Ops[0], Ops.size());
       if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
         Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
                              DstVecSize, DstVecEVT);
@@ -2896,7 +2904,7 @@ SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
   // this operation.
   if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 
       RHS.getOpcode() == ISD::VBUILD_VECTOR) {
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
       SDOperand LHSOp = LHS.getOperand(i);
       SDOperand RHSOp = RHS.getOperand(i);
@@ -2927,7 +2935,7 @@ SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
     if (Ops.size() == LHS.getNumOperands()-2) {
       Ops.push_back(*(LHS.Val->op_end()-2));
       Ops.push_back(*(LHS.Val->op_end()-1));
-      return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+      return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
     }
   }
   
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 22f6c7c074..906d71849e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -241,7 +241,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
     assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
     if (NumEltsGrowth > 1) {
       // Renumber the elements.
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
         SDOperand InOp = Mask.getOperand(i);
         for (unsigned j = 0; j != NumEltsGrowth; ++j) {
@@ -253,7 +253,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
           }
         }
       }
-      Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
+      Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
     }
     VT = NVT;
     break;
@@ -666,7 +666,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           cast<StringSDNode>(Node->getOperand(4))->getValue();
         unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
 
-        std::vector<SDOperand> Ops;
+        SmallVector<SDOperand, 8> Ops;
         Ops.push_back(Tmp1);  // chain
         SDOperand LineOp = Node->getOperand(1);
         SDOperand ColOp = Node->getOperand(2);
@@ -675,13 +675,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           Ops.push_back(LineOp);  // line #
           Ops.push_back(ColOp);  // col #
           Ops.push_back(DAG.getConstant(SrcFile, MVT::i32));  // source file id
-          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
         } else {
           unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
           unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
           unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
           Ops.push_back(DAG.getConstant(ID, MVT::i32));
-          Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
+          Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
         }
       } else {
         Result = Tmp1;  // chain
@@ -889,14 +889,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // We generate a shuffle of InVec and ScVec, so the shuffle mask should
         // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
         // the RHS.
-        std::vector<SDOperand> ShufOps;
+        SmallVector<SDOperand, 8> ShufOps;
         for (unsigned i = 0; i != NumElts; ++i) {
           if (i != InsertPos->getValue())
             ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
           else
             ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
         }
-        SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
+        SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
+                                         &ShufOps[0], ShufOps.size());
         
         Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
                              Tmp1, ScVec, ShufMask);
@@ -985,7 +986,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       MVT::ValueType PtrVT = TLI.getPointerTy();
       SDOperand Mask = Node->getOperand(2);
       unsigned NumElems = Mask.getNumOperands();
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand,8> Ops;
       for (unsigned i = 0; i != NumElems; ++i) {
         SDOperand Arg = Mask.getOperand(i);
         if (Arg.getOpcode() == ISD::UNDEF) {
@@ -1001,7 +1002,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
                                       DAG.getConstant(Idx - NumElems, PtrVT)));
         }
       }
-      Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+      Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
       break;
     }
     case TargetLowering::Promote: {
@@ -2149,7 +2150,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       assert(MVT::isVector(Node->getValueType(0)) &&
              "Cannot expand this binary operator!");
       // Expand the operation into a bunch of nasty scalar code.
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
       MVT::ValueType PtrVT = TLI.getPointerTy();
       for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
@@ -2159,7 +2160,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
         Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
       }
-      Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
+      Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 
+                           &Ops[0], Ops.size());
       break;
     }
     case TargetLowering::Promote: {
@@ -3556,7 +3558,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
       MVT::getIntVectorWithNumElements(NumElems);
     SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
     std::vector<SDOperand> ZeroVec(NumElems, Zero);
-    SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
+    SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+                                      &ZeroVec[0], ZeroVec.size());
 
     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
     if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
@@ -3586,12 +3589,13 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
         MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
       i += NumElems;
     }
-    SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+    SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+                                        &MaskVec[0], MaskVec.size());
 
     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
     if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
         isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
             E = Values.end(); I != E; ++I) {
         SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
@@ -3601,7 +3605,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
       Ops.push_back(ShuffleMask);
 
       // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
+      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 
+                         &Ops[0], Ops.size());
     }
   }
   
@@ -3613,7 +3618,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   SDOperand FIPtr = CreateStackTemporary(VT);
   
   // Emit a store of each element to the stack slot.
-  std::vector<SDOperand> Stores;
+  SmallVector<SDOperand, 8> Stores;
   unsigned TypeByteSize = 
     MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
   unsigned VectorSize = MVT::getSizeInBits(VT)/8;
@@ -3634,7 +3639,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   
   SDOperand StoreChain;
   if (!Stores.empty())    // Not all undef elements?
-    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                             &Stores[0], Stores.size());
   else
     StoreChain = DAG.getEntryNode();
   
@@ -3658,12 +3664,9 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
   SDOperand LHSL, LHSH;
   ExpandOp(Op, LHSL, LHSH);
 
-  std::vector<SDOperand> Ops;
-  Ops.push_back(LHSL);
-  Ops.push_back(LHSH);
-  Ops.push_back(Amt);
+  SDOperand Ops[] = { LHSL, LHSH, Amt };
   std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
-  Lo = DAG.getNode(NodeOp, VTs, Ops);
+  Lo = DAG.getNode(NodeOp, VTs, Ops, 3);
   Hi = Lo.getValue(1);
 }
 
@@ -4634,21 +4637,21 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     ExpandOp(Node->getOperand(0), LHSL, LHSH);
     ExpandOp(Node->getOperand(1), RHSL, RHSH);
     std::vector<MVT::ValueType> VTs;
-    std::vector<SDOperand> LoOps, HiOps;
+    SDOperand LoOps[2], HiOps[2];
     VTs.push_back(LHSL.getValueType());
     VTs.push_back(MVT::Flag);
-    LoOps.push_back(LHSL);
-    LoOps.push_back(RHSL);
-    HiOps.push_back(LHSH);
-    HiOps.push_back(RHSH);
+    LoOps[0] = LHSL;
+    LoOps[1] = RHSL;
+    HiOps[0] = LHSH;
+    HiOps[1] = RHSH;
     if (Node->getOpcode() == ISD::ADD) {
-      Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
-      HiOps.push_back(Lo.getValue(1));
-      Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
+      Lo = DAG.getNode(ISD::ADDC, VTs, LoOps, 2);
+      HiOps[2] = Lo.getValue(1);
+      Hi = DAG.getNode(ISD::ADDE, VTs, HiOps, 3);
     } else {
-      Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
-      HiOps.push_back(Lo.getValue(1));
-      Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
+      Lo = DAG.getNode(ISD::SUBC, VTs, LoOps, 2);
+      HiOps[2] = Lo.getValue(1);
+      Hi = DAG.getNode(ISD::SUBE, VTs, HiOps, 3);
     }
     break;
   }
@@ -4732,15 +4735,17 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
 #endif
     assert(0 && "Unhandled operation in SplitVectorOp!");
   case ISD::VBUILD_VECTOR: {
-    std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
+    SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 
+                                    Node->op_begin()+NewNumElts);
     LoOps.push_back(NewNumEltsNode);
     LoOps.push_back(TypeNode);
-    Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
+    Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
 
-    std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
+    SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 
+                                    Node->op_end()-2);
     HiOps.push_back(NewNumEltsNode);
     HiOps.push_back(TypeNode);
-    Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
+    Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
     break;
   }
   case ISD::VADD:
@@ -4891,8 +4896,8 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
       if (AllUndef) {
         Result = DAG.getNode(ISD::UNDEF, NewVT);
       } else {
-        std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
-        Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
+        Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
+                             Node->getNumOperands()-2);
       }
     }
     break;
@@ -4920,7 +4925,9 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
       std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
                                          Node->getOperand(2).Val->op_end()-2);
       MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
-      SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
+      SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
+                                 Node->getOperand(2).Val->op_begin(),
+                                 Node->getOperand(2).Val->getNumOperands()-2);
       
       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
                            PackVectorOp(Node->getOperand(0), NewVT),
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 154a6ca107..c6e2057445 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1539,16 +1539,11 @@ SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
 SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT,
                                    SDOperand Chain, SDOperand Ptr, SDOperand SV,
                                    MVT::ValueType EVT) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(4);
-  Ops.push_back(Chain);
-  Ops.push_back(Ptr);
-  Ops.push_back(SV);
-  Ops.push_back(getValueType(EVT));
+  SDOperand Ops[] = { Chain, Ptr, SV, getValueType(EVT) };
   std::vector<MVT::ValueType> VTs;
   VTs.reserve(2);
   VTs.push_back(VT); VTs.push_back(MVT::Other);  // Add token chain.
-  return getNode(Opcode, VTs, Ops);
+  return getNode(Opcode, VTs, Ops, 4);
 }
 
 SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
@@ -1565,15 +1560,11 @@ SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
 SDOperand SelectionDAG::getVAArg(MVT::ValueType VT,
                                  SDOperand Chain, SDOperand Ptr,
                                  SDOperand SV) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(3);
-  Ops.push_back(Chain);
-  Ops.push_back(Ptr);
-  Ops.push_back(SV);
+  SDOperand Ops[] = { Chain, Ptr, SV };
   std::vector<MVT::ValueType> VTs;
   VTs.reserve(2);
   VTs.push_back(VT); VTs.push_back(MVT::Other);  // Add token chain.
-  return getNode(ISD::VAARG, VTs, Ops);
+  return getNode(ISD::VAARG, VTs, Ops, 3);
 }
 
 SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
@@ -1719,17 +1710,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode,
   return SDOperand(N, 0);
 }
 
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
-                                std::vector<SDOperand> &Ops) {
-  return getNode(Opcode, VT, &Ops[0], Ops.size());
-}
-
-SDOperand SelectionDAG::getNode(unsigned Opcode, 
-                                std::vector<MVT::ValueType> &ResultTys,
-                                std::vector<SDOperand> &Ops) {
-  return getNode(Opcode, ResultTys, &Ops[0], Ops.size());
-}
-
 
 MVT::ValueType *SelectionDAG::getNodeValueTypes(MVT::ValueType VT) {
   return SDNode::getValueTypeList(VT);
@@ -2233,59 +2213,33 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
                                     SDOperand Op1, SDOperand Op2, SDOperand Op3,
                                     SDOperand Op4, SDOperand Op5,
                                     SDOperand Op6) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(6);
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 6).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
                                     SDOperand Op1, SDOperand Op2, SDOperand Op3,
                                     SDOperand Op4, SDOperand Op5, SDOperand Op6,
                                     SDOperand Op7) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(7);
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  Ops.push_back(Op7);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 7).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
                                     SDOperand Op1, SDOperand Op2, SDOperand Op3,
                                     SDOperand Op4, SDOperand Op5, SDOperand Op6,
                                     SDOperand Op7, SDOperand Op8) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(8);
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  Ops.push_back(Op7);
-  Ops.push_back(Op8);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 8).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
-                                    std::vector<SDOperand> &Ops) {
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+                                    const SDOperand *Ops, unsigned NumOps) {
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, NumOps).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1) {
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, &Op1, 1).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2293,10 +2247,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 2).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2304,11 +2256,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 3).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2317,12 +2266,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 4).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2331,13 +2276,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 5).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2346,14 +2286,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+  return getNode(ISD