diff options
| author | Chad Rosier <mcrosier@apple.com> | 2012-02-17 01:21:28 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-02-17 01:21:28 +0000 |
| commit | b8703fe265d44a3eb909c289cb5d31b840ca893c (patch) | |
| tree | c6131921ee44791d64c0e6adbe610f4de068f74e | |
| parent | 29879d7f86cac0f6a546675c5172a22ab7176519 (diff) | |
[fast-isel] Add support for returning non-legal types with no sign- or zero-
entend flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-ret.ll | 9 |
2 files changed, 15 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 21c1f86442..51c44d0adb 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -2037,14 +2037,14 @@ bool ARMFastISel::SelectRet(const Instruction *I) { if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) return false; - if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) - return false; - assert(DestVT == MVT::i32 && "ARM should always ext to i32"); - bool isZExt = Outs[0].Flags.isZExt(); - SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, isZExt); - if (SrcReg == 0) return false; + // Perform extension if flagged as either zext or sext. Otherwise, do + // nothing. + if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { + SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt()); + if (SrcReg == 0) return false; + } } // Make the copy. diff --git a/test/CodeGen/ARM/fast-isel-ret.ll b/test/CodeGen/ARM/fast-isel-ret.ll index 175cd9034c..689b169ee3 100644 --- a/test/CodeGen/ARM/fast-isel-ret.ll +++ b/test/CodeGen/ARM/fast-isel-ret.ll @@ -46,3 +46,12 @@ entry: ; CHECK: bx lr ret i16 %a } + +define i16 @ret6(i16 %a) nounwind uwtable ssp { +entry: +; CHECK: ret6 +; CHECK-NOT: uxth +; CHECK-NOT: sxth +; CHECK: bx lr + ret i16 %a +} |