diff options
| author | Nicolas Geoffray <nicolas.geoffray@lip6.fr> | 2008-10-25 15:22:06 +0000 |
|---|---|---|
| committer | Nicolas Geoffray <nicolas.geoffray@lip6.fr> | 2008-10-25 15:22:06 +0000 |
| commit | b74f370e437de31b53496e86f024b533ee8ec91b (patch) | |
| tree | 1f4f92ecc9f9d3176bfd7c450e8e8a2cfb79c82b | |
| parent | b7e1a4f70dfe6be901216a73c09d57856cec1041 (diff) | |
Generate code for TLS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58141 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 17 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 9 |
3 files changed, 27 insertions, 4 deletions
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 729e4b663e..2fe64273b1 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -527,6 +527,23 @@ void Emitter::emitInstruction(const MachineInstr &MI, case X86::DWARF_LOC: case X86::FP_REG_KILL: break; + case X86::TLS_tp: { + MCE.emitByte(BaseOpcode); + unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg()); + MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); + emitConstant(0, 4); + break; + } + case X86::TLS_gs_ri: { + MCE.emitByte(BaseOpcode); + unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg()); + MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); + GlobalValue* GV = MI.getOperand(1).getGlobal(); + unsigned rt = Is64BitMode ? X86::reloc_pcrel_word + : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); + emitGlobalAddress(GV, rt); + break; + } case X86::MOVPC32r: { // This emits the "call" portion of this pseudo instruction. MCE.emitByte(BaseOpcode); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 2db1448fd7..04f10c0088 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2798,6 +2798,11 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); break; } + case X86::TLS_tp: + case X86::TLS_gs_ri: + FinalSize += 2; + FinalSize += sizeGlobalAddress(false); + break; } CurOp = NumOps; break; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e23bc704b0..128f12de77 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2618,14 +2618,15 @@ def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>; let AddedComplexity = 15 in -def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src), +def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src), "movl\t%gs:${src:mem}, $dst", [(set GR32:$dst, - (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>; + (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>, + SegGS; -def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins), +def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins), "movl\t%gs:0, $dst", - [(set GR32:$dst, X86TLStp)]>; + [(set GR32:$dst, X86TLStp)]>, SegGS; //===----------------------------------------------------------------------===// // DWARF Pseudo Instructions |