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authorAnton Korobeynikov <asl@math.spbu.ru>2009-07-16 13:31:28 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-07-16 13:31:28 +0000
commitb573f99ab71413c718086eed89490635d52c685c (patch)
tree4fade225728963e603fc3f12bb160137e170fdc2
parent26ba0b1ec505bf6d6b8845e039690f9a06323ceb (diff)
Add xor reg-reg pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/SystemZ/SystemZInstrInfo.td7
-rw-r--r--test/CodeGen/SystemZ/02-RetXor.ll6
-rw-r--r--test/CodeGen/SystemZ/02-RetXorImm.ll6
3 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 66b2db972c..c4121fe604 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -77,5 +77,12 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
}
// FIXME: provide patterns for masked or-with-imm
+let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
+// FIXME: Provide proper encoding!
+def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+ "xgr\t{$dst, $src2}",
+ [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
+}
+
} // Defs = [PSW]
} // isTwoAddress = 1
diff --git a/test/CodeGen/SystemZ/02-RetXor.ll b/test/CodeGen/SystemZ/02-RetXor.ll
new file mode 100644
index 0000000000..b15d9460a6
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetXor.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = xor i64 %a, %b
+ ret i64 %c
+} \ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetXorImm.ll b/test/CodeGen/SystemZ/02-RetXorImm.ll
new file mode 100644
index 0000000000..f1f835a0ed
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetXorImm.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = xor i64 %a, 1
+ ret i64 %c
+} \ No newline at end of file