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authorMisha Brukman <brukman+llvm@gmail.com>2004-08-10 18:07:55 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2004-08-10 18:07:55 +0000
commita91f53634ccec6df7e63d0488cc6b6c457829215 (patch)
treee64f8c2e45ec26b96060f03466de04c6d2ac3540
parent7b717764015792dffac72bb963f67f8c510a5988 (diff)
Fix DForm_4: format is `op r, r, i'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15613 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCInstrFormats.td5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 7e54786f8c..84d54960f3 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -139,7 +139,6 @@ class DForm_2<string name, bits<6> opcode, bit ppc64, bit vmx>
class DForm_2_r0<string name, bits<6> opcode, bit ppc64, bit vmx>
: DForm_base<name, opcode, ppc64, vmx> {
let Arg1Type = Gpr0.Value;
- let B = 0;
}
// Currently we make the use/def reg distinction in ISel, not tablegen
@@ -147,7 +146,9 @@ class DForm_3<string name, bits<6> opcode, bit ppc64, bit vmx>
: DForm_1<name, opcode, ppc64, vmx>;
class DForm_4<string name, bits<6> opcode, bit ppc64, bit vmx>
- : DForm_1<name, opcode, ppc64, vmx>;
+ : DForm_base<name, opcode, ppc64, vmx> {
+ let Arg2Type = Zimm16.Value;
+}
class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx>
: DForm_1<name, opcode, ppc64, vmx> {