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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-17 09:31:09 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-17 09:31:09 +0000 |
| commit | a16d441430440d9255fe16441cea7a38e8f3c461 (patch) | |
| tree | 4a1d6524604cff7420e0425ab8badf5a0ee0309b | |
| parent | a7f99f28a71635e83d85c68c47ca0fc20ec68400 (diff) | |
Fix warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148301 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 8f69b0e314..ab5a8de92b 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6245,7 +6245,7 @@ bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point // because the legalization of N did not happen yet. - if (Idx >= NumElems/2 && VT.getSizeInBits() == 256) + if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256) return false; // Skip one more bit_convert if necessary |