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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-09-03 00:47:05 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-09-03 00:47:05 +0000
commit9f63615b17506c954ef21c6e681a94ffb3534af8 (patch)
tree71b306e2194f90f814dfd44e6aea1ea415233717
parentd01ef7d97844ac3c85efdc5816b6d03353fca183 (diff)
Add AVX version of a SSE4.1 VPBLENDVB pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139072 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86InstrSSE.td6
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 1d3b81c87f..601ec03521 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -5843,6 +5843,10 @@ defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
memopv32i8, int_x86_avx_blendv_ps_256>;
+def : Pat<(X86pblendv VR128:$src1, VR128:$src2, VR128:$src3),
+ (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
+ Requires<[HasAVX]>;
+
/// SS41I_ternary_int - SSE 4.1 ternary operator
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
@@ -5868,7 +5872,7 @@ defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
- (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
+ (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
let Predicates = [HasAVX] in
def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),