diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-25 18:30:18 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-25 18:30:18 +0000 |
| commit | 99906830e82cf70dbcbed22237c7bd24f9d9ffdb (patch) | |
| tree | 7758dbb96d8aa0a3ff8ff781dd19c65d6ccf1a15 | |
| parent | cf847bfa6f01645d023fbc959c207259ecb48391 (diff) | |
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb1.txt | 31 |
2 files changed, 32 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 83a8f80060..0d945fdf59 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction16(Insn, 3, 4); diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index d07cd84abc..3e0722d32e 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -29,6 +29,29 @@ 0x42 0x44 #------------------------------------------------------------------------------ +# ADD (SP plus immediate) +#------------------------------------------------------------------------------ +# CHECK: add sp, #508 +# CHECK: add sp, #4 +# CHECK: add r2, sp, #8 +# CHECK: add r2, sp, #1020 + +0x7f 0xb0 +0x01 0xb0 +0x02 0xaa +0xff 0xaa + + +#------------------------------------------------------------------------------ +# ADD (SP plus register) +#------------------------------------------------------------------------------ +# CHECK: add sp, r3 +# CHECK: add r2, sp, r2 + +0x9d 0x44 +0x6a 0x44 + +#------------------------------------------------------------------------------ # ASR (immediate) #------------------------------------------------------------------------------ # CHECK: asrs r2, r3, #32 @@ -442,6 +465,14 @@ 0xd1 0x1a +#------------------------------------------------------------------------------ +# SUB (SP minus immediate) +#------------------------------------------------------------------------------ +# CHECK: sub sp, #12 +# CHECK: sub sp, #508 + +0x83 0xb0 +0xff 0xb0 #------------------------------------------------------------------------------ # SVC |