diff options
| author | Bill Wendling <isanbard@gmail.com> | 2009-04-29 23:29:43 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2009-04-29 23:29:43 +0000 |
| commit | 98a366d547772010e94609e4584489b3e5ce0043 (patch) | |
| tree | 740060aedf3541a695c8ee54326cd88874936263 | |
| parent | b587f9662a7b6f00f9ce48ddf2dea1a4fb18a6db (diff) | |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
81 files changed, 377 insertions, 251 deletions
diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index 3f61d74e13..727fd61963 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -16,9 +16,10 @@ #ifndef LLVM_CODEGEN_ASMPRINTER_H #define LLVM_CODEGEN_ASMPRINTER_H +#include "llvm/ADT/DenseMap.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Support/DataTypes.h" -#include "llvm/ADT/DenseMap.h" +#include "llvm/Target/TargetMachine.h" #include <set> namespace llvm { @@ -66,7 +67,7 @@ namespace llvm { std::set<const GlobalValue*> ExtWeakSymbols; /// OptLevel - Generating code at a specific optimization level. - unsigned OptLevel; + CodeGenOpt::Level OptLevel; public: /// Output stream on which we're printing assembly code. /// @@ -111,7 +112,7 @@ namespace llvm { protected: explicit AsmPrinter(raw_ostream &o, TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V); + const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V); public: virtual ~AsmPrinter(); diff --git a/include/llvm/CodeGen/DwarfWriter.h b/include/llvm/CodeGen/DwarfWriter.h index 5641407001..e4e485039e 100644 --- a/include/llvm/CodeGen/DwarfWriter.h +++ b/include/llvm/CodeGen/DwarfWriter.h @@ -21,6 +21,7 @@ #define LLVM_CODEGEN_DWARFWRITER_H #include "llvm/Pass.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { @@ -81,7 +82,7 @@ public: void EndFunction(MachineFunction *MF); /// ValidDebugInfo - Return true if V represents valid debug info value. - bool ValidDebugInfo(Value *V, unsigned OptLevel); + bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel); /// RecordSourceLine - Register a source line with debug info. Returns a /// unique label ID used to generate a label and provide correspondence to diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h index 84d9819c2d..a231f49d81 100644 --- a/include/llvm/CodeGen/LinkAllCodegenComponents.h +++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h @@ -18,6 +18,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/GCs.h" +#include "llvm/Target/TargetMachine.h" namespace { struct ForceCodegenLinking { @@ -42,11 +43,11 @@ namespace { llvm::linkOcamlGC(); llvm::linkShadowStackGC(); - (void) llvm::createBURRListDAGScheduler(NULL, 3); - (void) llvm::createTDRRListDAGScheduler(NULL, 3); - (void) llvm::createTDListDAGScheduler(NULL, 3); - (void) llvm::createFastDAGScheduler(NULL, 3); - (void) llvm::createDefaultScheduler(NULL, 3); + (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default); + (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default); + (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default); + (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default); + (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default); } } ForceCodegenLinking; // Force link by creating a global definition. diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index e02dc7a392..1cf64a09a7 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -16,6 +16,7 @@ #define LLVM_CODEGENSCHEDULERREGISTRY_H #include "llvm/CodeGen/MachinePassRegistry.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { @@ -32,7 +33,8 @@ class MachineBasicBlock; class RegisterScheduler : public MachinePassRegistryNode { public: - typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned); + typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, + CodeGenOpt::Level); static MachinePassRegistry Registry; @@ -64,27 +66,27 @@ public: /// createBURRListDAGScheduler - This creates a bottom up register usage /// reduction list scheduler. ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); /// createFastDAGScheduler - This creates a "fast" scheduler. /// ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); } // end namespace llvm diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 90603769d9..74aa8ff820 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -20,7 +20,7 @@ #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/StringMap.h" #include "llvm/CodeGen/SelectionDAGNodes.h" - +#include "llvm/Target/TargetMachine.h" #include <cassert> #include <vector> #include <map> @@ -30,7 +30,6 @@ namespace llvm { class AliasAnalysis; class TargetLowering; -class TargetMachine; class MachineModuleInfo; class DwarfWriter; class MachineFunction; @@ -202,7 +201,8 @@ public: /// certain types of nodes together, or eliminating superfluous nodes. The /// Level argument controls whether Combine is allowed to produce nodes and /// types that are illegal on the target. - void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel); + void Combine(CombineLevel Level, AliasAnalysis &AA, + CodeGenOpt::Level OptLevel); /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that /// only uses types natively supported by the target. Returns "true" if it @@ -218,7 +218,7 @@ public: /// /// Note that this is an involved process that may invalidate pointers into /// the graph. - void Legalize(bool TypesNeedLegalizing, unsigned OptLevel); + void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel); /// RemoveDeadNodes - This method deletes all unreachable nodes in the /// SelectionDAG. diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index d8802c7d9d..05a047563a 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -51,10 +51,11 @@ public: MachineBasicBlock *BB; AliasAnalysis *AA; GCFunctionInfo *GFI; - unsigned OptLevel; + CodeGenOpt::Level OptLevel; static char ID; - explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3); + explicit SelectionDAGISel(TargetMachine &tm, + CodeGenOpt::Level OL = CodeGenOpt::Default); virtual ~SelectionDAGISel(); TargetLowering &getTargetLowering() { return TLI; } diff --git a/include/llvm/ExecutionEngine/ExecutionEngine.h b/include/llvm/ExecutionEngine/ExecutionEngine.h index 014473adae..5df11f33ba 100644 --- a/include/llvm/ExecutionEngine/ExecutionEngine.h +++ b/include/llvm/ExecutionEngine/ExecutionEngine.h @@ -18,8 +18,9 @@ #include <vector> #include <map> #include <string> -#include "llvm/System/Mutex.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/System/Mutex.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { @@ -84,7 +85,7 @@ protected: // libraries, the JIT and Interpreter set these functions to ctor pointers // at startup time if they are linked in. typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); static EECtorFn JITCtor, InterpCtor; /// LazyFunctionCreator - If an unknown function is needed, this function @@ -114,7 +115,8 @@ public: static ExecutionEngine *create(ModuleProvider *MP, bool ForceInterpreter = false, std::string *ErrorStr = 0, - unsigned OptLevel = 3); + CodeGenOpt::Level OptLevel = + CodeGenOpt::Default); /// create - This is the factory method for creating an execution engine which /// is appropriate for the current machine. This takes ownership of the @@ -127,10 +129,9 @@ public: static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *ErrorStr = 0, JITMemoryManager *JMM = 0, - unsigned OptLevel = 3); - - - + CodeGenOpt::Level OptLevel = + CodeGenOpt::Default); + /// addModuleProvider - Add a ModuleProvider to the list of modules that we /// can JIT from. Note that this takes ownership of the ModuleProvider: when /// the ExecutionEngine is destroyed, it destroys the MP as well. diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index ba688b48de..8afd71f721 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -68,6 +68,19 @@ namespace FileModel { }; } +// Code generation optimization level. +namespace CodeGenOpt { + enum Level { + Default, + None, + One, + Two, + Size, + Aggressive, + LTO + }; +} + //===----------------------------------------------------------------------===// /// /// TargetMachine - Primary interface to the complete machine description for @@ -213,7 +226,7 @@ public: virtual FileModel::Model addPassesToEmitFile(PassManagerBase &, raw_ostream &, CodeGenFileType, - unsigned /* OptLevel */) { + CodeGenOpt::Level) { return FileModel::None; } @@ -223,7 +236,7 @@ public: /// virtual bool addPassesToEmitFileFinish(PassManagerBase &, MachineCodeEmitter *, - unsigned /* OptLevel */) { + CodeGenOpt::Level) { return true; } @@ -235,7 +248,7 @@ public: /// virtual bool addPassesToEmitMachineCode(PassManagerBase &, MachineCodeEmitter &, - unsigned /* OptLevel */) { + CodeGenOpt::Level) { return true; } @@ -245,7 +258,7 @@ public: virtual bool WantsWholeFile() const { return false; } virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &, CodeGenFileType, - unsigned /* OptLevel */) { + CodeGenOpt::Level) { return true; } }; @@ -260,13 +273,13 @@ protected: // Can only create subclasses. /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for /// both emitting to assembly files or machine code output. /// - bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */); + bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level); public: /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code - /// generation. If OptLevel is 0, the code generator should emit code as fast + /// generation. If OptLevel is None, the code generator should emit code as fast /// as possible, though the generated code may be less efficient. This method /// should return FileModel::Error if emission of this file type is not /// supported. @@ -278,7 +291,7 @@ public: virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, CodeGenFileType FileType, - unsigned OptLevel); + CodeGenOpt::Level); /// addPassesToEmitFileFinish - If the passes to emit the specified file had /// to be split up (e.g., to add an object writer pass), this method can be @@ -286,7 +299,7 @@ public: /// virtual bool addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, - unsigned OptLevel); + CodeGenOpt::Level); /// addPassesToEmitMachineCode - Add passes to the specified pass manager to /// get machine code emitted. This uses a MachineCodeEmitter object to handle @@ -296,21 +309,21 @@ public: /// virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, - unsigned OptLevel); + CodeGenOpt::Level); /// Target-Independent Code Generator Pass Configuration Options. /// addInstSelector - This method should add any "last minute" LLVM->LLVM /// passes, then install an instruction selector pass, which converts from /// LLVM code to machine instructions. - virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) { + virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { return true; } /// addPreRegAllocPasses - This method may be implemented by targets that want /// to run passes immediately before register allocation. This should return /// true if -print-machineinstrs should print after these passes. - virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) { + virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { return false; } @@ -318,14 +331,14 @@ public: /// want to run passes after register allocation but before prolog-epilog /// insertion. This should return true if -print-machineinstrs should print /// after these passes. - virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) { + virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { return false; } /// addPreEmitPass - This pass may be implemented by targets that want to run /// passes immediately before machine code is emitted. This should return /// true if -print-machineinstrs should print out the code after the passes. - virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) { + virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { return false; } @@ -333,7 +346,7 @@ public: /// addAssemblyEmitter - This pass should be overridden by the target to add /// the asmprinter, if asm emission is supported. If this is not supported, /// 'true' should be returned. - virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */, + virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level, bool /* VerboseAsmDefault */, raw_ostream &) { return true; } @@ -341,7 +354,7 @@ public: /// addCodeEmitter - This pass should be overridden by the target to add a /// code emitter, if supported. If this is not supported, 'true' should be /// returned. If DumpAsm is true, the generated assembly is printed to cerr. - virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */, + virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, bool /*DumpAsm*/, MachineCodeEmitter &) { return true; } @@ -350,7 +363,7 @@ public: /// a code emitter (without setting flags), if supported. If this is not /// supported, 'true' should be returned. If DumpAsm is true, the generated /// assembly is printed to cerr. - virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */, + virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level, bool /*DumpAsm*/, MachineCodeEmitter &) { return true; } diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index e0a526c372..319bbdbe65 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -27,7 +27,6 @@ #include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/SmallPtrSet.h" @@ -42,7 +41,7 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."), char AsmPrinter::ID = 0; AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm, - const TargetAsmInfo *T, unsigned OL, bool VDef) + const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef) : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), IsInTextSection(false) diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp index 5d6a70f622..499f800d7e 100644 --- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp @@ -3351,7 +3351,7 @@ public: } /// ValidDebugInfo - Return true if V represents valid debug info value. - bool ValidDebugInfo(Value *V, unsigned OptLevel) { + bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) { if (!V) return false; @@ -3393,7 +3393,7 @@ public: case DW_TAG_lexical_block: /// FIXME. This interfers with the qualitfy of generated code when /// during optimization. - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) return false; default: break; @@ -4731,7 +4731,7 @@ void DwarfWriter::EndFunction(MachineFunction *MF) { } /// ValidDebugInfo - Return true if V represents valid debug info value. -bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) { +bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) { return DD && DD->ValidDebugInfo(V, OptLevel); } diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 92aeb64c7d..faaa41b68b 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -55,7 +55,7 @@ FileModel::Model LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, CodeGenFileType FileType, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { // Add common CodeGen passes. if (addCommonCodeGenPasses(PM, OptLevel)) return FileModel::Error; @@ -69,7 +69,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) PM.add(createLoopAlignerPass()); switch (FileType) { @@ -94,7 +94,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, /// finish up adding passes to emit the file, if necessary. bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { if (MCE) addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE); @@ -114,7 +114,7 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, /// bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { // Add common CodeGen passes. if (addCommonCodeGenPasses(PM, OptLevel)) return true; @@ -132,15 +132,15 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, return false; // success! } -/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for -/// both emitting to assembly files or machine code output. +/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both +/// emitting to assembly files or machine code output. /// bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { // Standard LLVM-Level Passes. // Run loop strength reduction before anything else. - if (OptLevel != 0) { + if (OptLevel != CodeGenOpt::None) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs())); @@ -154,7 +154,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createStackProtectorPass(getTargetLowering())); @@ -168,7 +168,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, // Enable FastISel with -fast, but allow that to be overridden. if (EnableFastISelOption == cl::BOU_TRUE || - (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE)) + (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE)) EnableFastISel = true; // Ask the target for an isel. @@ -179,7 +179,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (OptLevel != 0) { + if (OptLevel != CodeGenOpt::None) { PM.add(createMachineLICMPass()); PM.add(createMachineSinkingPass()); } @@ -192,7 +192,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, PM.add(createRegisterAllocator()); // Perform stack slot coloring. - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) PM.add(createStackSlotColoringPass()); if (PrintMachineCode) // Print the register-allocated code @@ -217,7 +217,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, PM.add(createMachineFunctionPrinterPass(cerr)); // Second pass scheduler. - if (OptLevel != 0 && !DisablePostRAScheduler) { + if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) { PM.add(createPostRAScheduler()); if (PrintMachineCode) @@ -225,7 +225,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, } // Branch folding must be run after regalloc and prolog/epilog insertion. - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); if (PrintMachineCode) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 226699b672..1378f25387 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -57,7 +57,7 @@ namespace { SelectionDAG &DAG; const TargetLowering &TLI; CombineLevel Level; - unsigned OptLevel; + CodeGenOpt::Level OptLevel; bool LegalOperations; bool LegalTypes; @@ -254,7 +254,7 @@ namespace { } public: - DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL) + DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), @@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { SDValue Ptr = LD->getBasePtr(); // Try to infer better alignment information than the load already has. - if (OptLevel != 0 && LD->isUnindexed()) { + if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > LD->getAlignment()) return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), @@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { SDValue Ptr = ST->getBasePtr(); // Try to infer better alignment information than the store already has. - if (OptLevel != 0 && ST->isUnindexed()) { + if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > ST->getAlignment()) return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, @@ -6093,7 +6093,7 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { // SelectionDAG::Combine - This is the entry point for the file. // void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { /// run - This is the main entry point to this class. /// DAGCombiner(*this, AA, OptLevel).Run(Level); diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index a7801ebccf..09ac586dd5 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) { default: break; case Intrinsic::dbg_stoppoint: { DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) { + if (DW && DW->ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) { DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); std::string Dir, FN; unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), @@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_start: { DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); - if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) { + if (DW && DW->ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) { unsigned ID = DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); @@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_end: { DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); - if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) { + if (DW && DW->ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) { unsigned ID = 0; DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { @@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) { DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI->getSubprogram(); - if (DW->ValidDebugInfo(SP, 0)) { + if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = DL; @@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) { case Intrinsic::dbg_declare: { DbgDeclareInst *DI = cast<DbgDeclareInst>(I); Value *Variable = DI->getVariable(); - if (DW && DW->ValidDebugInfo(Variable, 0)) { + if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) { // Determine the address of the declared object. Value *Address = DI->getAddress(); if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index efa62be36d..9c43065040 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -55,7 +55,7 @@ namespace { class VISIBILITY_HIDDEN SelectionDAGLegalize { TargetLowering &TLI; SelectionDAG &DAG; - unsigned OptLevel; + CodeGenOpt::Level OptLevel; bool TypesNeedLegalizing; // Libcall insertion helpers. @@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize { public: explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing, - unsigned ol); + CodeGenOpt::Level ol); /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of @@ -350,7 +350,7 @@ SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, } SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, - bool types, unsigned ol) + bool types, CodeGenOpt::Level ol) : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) { assert(MVT::LAST_VALUETYPE <= 32 && @@ -1276,7 +1276,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { unsigned Line = DSP->getLine(); unsigned Col = DSP->getColumn(); - if (OptLevel == 0) { + if (OptLevel == CodeGenOpt::None) { // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it // won't hurt anything. if (useDEBUG_LOC) { @@ -8571,7 +8571,8 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, // SelectionDAG::Legalize - This is the entry point for the file. // -void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) { +void SelectionDAG::Legalize(bool TypesNeedLegalizing, + CodeGenOpt::Level OptLevel) { /// run - This is the main entry point to this class. /// SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG(); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index c87820a97b..af73b28fae 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) { return new ScheduleDAGFast(*IS->MF); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 2ac934a0d0..c432534999 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() { /// new hazard recognizer. This scheduler takes ownership of the hazard /// recognizer and deletes it when done. ScheduleDAGSDNodes * -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) { return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index aecd02aba3..c97e2a8c86 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); @@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { } llvm::ScheduleDAGSDNodes * -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index afadd62caa..01d73b3ffb 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -45,7 +45,6 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/CommandLine.h" @@ -335,7 +334,8 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, DwarfWriter *DW = DAG.getDwarfWriter(); DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) { + if (DW && DW->ValidDebugInfo(SPI->getContext(), + CodeGenOpt::Default)) { DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); std::string Dir, FN; unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), @@ -354,7 +354,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI->getSubprogram(); - if (DW->ValidDebugInfo(SP, false)) { + if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) { DISubprogram Subprogram(cast<GlobalVariable>(SP)); DICompileUnit CU(Subprogram.getCompileUnit()); std::string Dir, FN; @@ -3899,7 +3899,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) { MachineFunction &MF = DAG.getMachineFunction(); - if (OptLevel == 0) + if (OptLevel == CodeGenOpt::None) DAG.setRoot(DAG.getDbgStopPoint(getRoot(), SPI.getLine(), SPI.getColumn(), @@ -3940,7 +3940,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) { // This is end of inlined function. Debugging information for // inlined function is not handled yet (only supported by FastISel). - if (OptLevel == 0) { + if (OptLevel == CodeGenOpt::None) { unsigned ID = DW->RecordInlinedFnEnd(Subprogram); if (ID != 0) // Returned ID is 0 if this is unbalanced "end of inlined @@ -3968,7 +3968,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Value *SP = FSI.getSubprogram(); if (SP && DW->ValidDebugInfo(SP, OptLevel)) { MachineFunction &MF = DAG.getMachineFunction(); - if (OptLevel == 0) { + if (OptLevel == CodeGenOpt::None) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = CurDebugLoc; @@ -4039,7 +4039,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; } case Intrinsic::dbg_declare: { - if (OptLevel == 0) { + if (OptLevel == CodeGenOpt::None) { DwarfWriter *DW = DAG.getDwarfWriter(); DbgDeclareInst &DI = cast<DbgDeclareInst>(I); Value *Variable = DI.getVariable(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h index 773f33938c..578aa591ce 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h @@ -23,6 +23,7 @@ #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Support/CallSite.h" +#include "llvm/Target/TargetMachine.h" #include <vector> #include <set> @@ -357,13 +358,14 @@ public: /// OptLevel - What optimization level we're generating code for. /// - unsigned OptLevel; + CodeGenOpt::Level OptLevel; /// GFI - Garbage collection metadata for the function. GCFunctionInfo *GFI; SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, - FunctionLoweringInfo &funcinfo, unsigned ol) + FunctionLoweringInfo &funcinfo, + CodeGenOpt::Level ol) : CurDebugLoc(DebugLoc::getUnknownLoc()), TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) { } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 37087ec6d5..4c934cd129 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -136,10 +136,10 @@ namespace llvm { /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { const TargetLowering &TLI = IS->getTargetLowering(); - if (OptLevel == 0) + if (OptLevel == CodeGenOpt::None) return createFastDAGScheduler(IS, OptLevel); if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) return createTDListDAGScheduler(IS, OptLevel); @@ -262,7 +262,7 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, // SelectionDAGISel code //===----------------------------------------------------------------------===// -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) : +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), FuncInfo(new FunctionLoweringInfo(TLI)), CurDAG(new SelectionDAG(TLI, *FuncInfo)), @@ -645,7 +645,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) ComputeLiveOutVRegInfo(); // Third, instruction select all of the operations to machine code, adding the diff --git a/lib/ExecutionEngine/ExecutionEngine.cpp b/lib/ExecutionEngine/ExecutionEngine.cpp index e64af9118d..9cd03dac27 100644 --- a/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/lib/ExecutionEngine/ExecutionEngine.cpp @@ -383,7 +383,7 @@ int ExecutionEngine::runFunctionAsMain(Function *Fn, ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP, bool ForceInterpreter, std::string *ErrorStr, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { ExecutionEngine *EE = 0; // Make sure we can resolve symbols in the program as well. The zero arg diff --git a/lib/ExecutionEngine/ExecutionEngineBindings.cpp b/lib/ExecutionEngine/ExecutionEngineBindings.cpp index 57467c2b81..0ef85dd036 100644 --- a/lib/ExecutionEngine/ExecutionEngineBindings.cpp +++ b/lib/ExecutionEngine/ExecutionEngineBindings.cpp @@ -114,7 +114,7 @@ int LLVMCreateInterpreter(LLVMExecutionEngineRef *OutInterp, int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT, LLVMModuleProviderRef MP, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, char **OutError) { std::string Error; if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0, diff --git a/lib/ExecutionEngine/Interpreter/Interpreter.cpp b/lib/ExecutionEngine/Interpreter/Interpreter.cpp index c05eeac086..ded65d5467 100644 --- a/lib/ExecutionEngine/Interpreter/Interpreter.cpp +++ b/lib/ExecutionEngine/Interpreter/Interpreter.cpp @@ -37,7 +37,7 @@ namespace llvm { /// create - Create a new interpreter object. This can never fail. /// ExecutionEngine *Interpreter::create(ModuleProvider *MP, std::string* ErrStr, - unsigned OptLevel /*unused*/) { + CodeGenOpt::Level OptLevel /*unused*/) { // Tell this ModuleProvide to materialize and release the module if (!MP->materializeModule(ErrStr)) // We got an error, just return 0 diff --git a/lib/ExecutionEngine/Interpreter/Interpreter.h b/lib/ExecutionEngine/Interpreter/Interpreter.h index 2e10e6b497..8a285ecb82 100644 --- a/lib/ExecutionEngine/Interpreter/Interpreter.h +++ b/lib/ExecutionEngine/Interpreter/Interpreter.h @@ -108,7 +108,7 @@ public: /// create - Create an interpreter ExecutionEngine. This can never fail. /// static ExecutionEngine *create(ModuleProvider *M, std::string *ErrorStr = 0, - unsigned OptLevel /*unused*/ = 3); + CodeGenOpt::Level = CodeGenOpt::Default); /// run - Start execution with the specified function and arguments. /// diff --git a/lib/ExecutionEngine/JIT/JIT.cpp b/lib/ExecutionEngine/JIT/JIT.cpp index 93203a257c..28ff253c37 100644 --- a/lib/ExecutionEngine/JIT/JIT.cpp +++ b/lib/ExecutionEngine/JIT/JIT.cpp @@ -196,7 +196,7 @@ void DarwinRegisterFrame(void* FrameBegin) { ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP, std::string *ErrorStr, JITMemoryManager *JMM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel); if (!EE) return 0; @@ -207,7 +207,7 @@ ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP, } JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji, - JITMemoryManager *JMM, unsigned OptLevel) + JITMemoryManager *JMM, CodeGenOpt::Level OptLevel) : ExecutionEngine(MP), TM(tm), TJI(tji) { setTargetData(TM.getTargetData()); @@ -272,7 +272,7 @@ void JIT::addModuleProvider(ModuleProvider *MP) { // Turn the machine code intermediate representation into bytes in memory // that may be executed. - if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) { + if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) { cerr << "Target does not support machine code emission!\n"; abort(); } @@ -305,7 +305,7 @@ Module *JIT::removeModuleProvider(ModuleProvider *MP, std::string *E) { // Turn the machine code intermediate representation into bytes in memory // that may be executed. - if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) { + if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) { cerr << "Target does not support machine code emission!\n"; abort(); } @@ -337,7 +337,7 @@ void JIT::deleteModuleProvider(ModuleProvider *MP, std::string *E) { // Turn the machine code intermediate representation into bytes in memory // that may be executed. - if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) { + if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) { cerr << "Target does not support machine code emission!\n"; abort(); } diff --git a/lib/ExecutionEngine/JIT/JIT.h b/lib/ExecutionEngine/JIT/JIT.h index b3ae82c58c..d5646063e9 100644 --- a/lib/ExecutionEngine/JIT/JIT.h +++ b/lib/ExecutionEngine/JIT/JIT.h @@ -55,7 +55,7 @@ class JIT : public ExecutionEngine { JITState *jitstate; JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji, - JITMemoryManager *JMM, unsigned OptLevel); + JITMemoryManager *JMM, CodeGenOpt::Level OptLevel); public: ~JIT(); @@ -71,7 +71,8 @@ public: /// for the current target. Otherwise, return null. /// static ExecutionEngine *create(ModuleProvider *MP, std::string *Err, - unsigned OptLevel = 3) { + CodeGenOpt::Level OptLevel = + CodeGenOpt::Default) { return createJIT(MP, Err, 0, OptLevel); } @@ -148,7 +149,8 @@ public: MachineCodeEmitter *getCodeEmitter() const { return MCE; } static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *Err, - JITMemoryManager *JMM, unsigned OptLevel); + JITMemoryManager *JMM, + CodeGenOpt::Level OptLevel); private: static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM); diff --git a/lib/ExecutionEngine/JIT/TargetSelect.cpp b/lib/ExecutionEngine/JIT/TargetSelect.cpp index 7edd0837d5..0f20819307 100644 --- a/lib/ExecutionEngine/JIT/TargetSelect.cpp +++ b/lib/ExecutionEngine/JIT/TargetSelect.cpp @@ -42,7 +42,8 @@ MAttrs("mattr", /// available for the current target. Otherwise, return null. /// ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr, - JITMemoryManager *JMM, unsigned OptLevel) { + JITMemoryManager *JMM, + CodeGenOpt::Level OptLevel) { const TargetMachineRegistry::entry *TheArch = MArch; if (TheArch == 0) { std::string Error; diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 63bb8f6073..b275d2a8d8 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -15,6 +15,7 @@ #ifndef TARGET_ARM_H #define TARGET_ARM_H +#include "llvm/Target/TargetMachine.h" #include <cassert> namespace llvm { @@ -91,7 +92,8 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { FunctionPass *createARMISelDag(ARMTargetMachine &TM); FunctionPass *createARMCodePrinterPass(raw_ostream &O, ARMTargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM, MachineCodeEmitter &MCE); FunctionPass *createARMLoadStoreOptimizationPass(); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index a2ee52e30d..a5ce86e9df 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -138,17 +138,20 @@ const TargetAsmInfo *ARMTargetMachine::createTargetAsmInfo() const { // Pass Pipeline Configuration -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { PM.add(createARMISelDag(*this)); return false; } -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb mode. - if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb()) + if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb()) PM.add(createARMLoadStoreOptimizationPass()); - if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb()) + if (OptLevel != CodeGenOpt::None && + !DisableIfConversion && !Subtarget.isThumb()) PM.add(createIfConverterPass()); PM.add(createARMConstantIslandPass()); @@ -156,7 +159,7 @@ bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { } bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { // Output assembly language. @@ -168,8 +171,10 @@ bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, } -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE) { +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + bool DumpAsm, + MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! if (DefRelocModel == Reloc::Default) setRelocationModel(Reloc::Static); @@ -186,7 +191,7 @@ bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, } bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // Machine code emitter pass for ARM. diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index cfb617867d..3f65f71bbe 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -41,7 +41,8 @@ protected: // set this functions to ctor pointer at startup time if they are linked in. typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, ARMTargetMachine &tm, - unsigned OptLevel, bool verbose); + CodeGenOpt::Level OptLevel, + bool verbose); static AsmPrinterCtorFn AsmPrinterCtor; public: @@ -69,14 +70,17 @@ public: virtual const TargetAsmInfo *createTargetAsmInfo() const; // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE); + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + bool DumpAsm, + MachineCodeEmitter &MCE); }; /// ThumbTargetMachine - Thumb target machine. diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index 6559a9d797..d5def375c0 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -81,7 +81,8 @@ namespace { bool InCPMode; public: explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL), InCPMode(false) { Subtarget = &TM.getSubtarget<ARMSubtarget>(); @@ -1061,7 +1062,8 @@ bool ARMAsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o, ARMTargetMachine &tm, - unsigned OptLevel, bool verbose) { + CodeGenOpt::Level OptLevel, + bool verbose) { return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h index 994edaa24c..853109ae34 100644 --- a/lib/Target/Alpha/Alpha.h +++ b/lib/Target/Alpha/Alpha.h @@ -15,18 +15,20 @@ #ifndef TARGET_ALPHA_H #define TARGET_ALPHA_H +#include "llvm/Target/TargetMachine.h" + namespace llvm { class AlphaTargetMachine; class FunctionPass; - class TargetMachine; class MachineCodeEmitter; class raw_ostream; FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM); FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS, TargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM); FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM, MachineCodeEmitter &MCE); diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 7a87612038..802a803670 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -77,25 +77,26 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS) //===----------------------------------------------------------------------===// bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { PM.add(createAlphaISelDag(*this)); return false; } bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { // Must run branch selection immediately preceding the asm printer PM.add(createAlphaBranchSelectionPass()); return false; } bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { PM.add(createAlphaLLRPPass(*this)); PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { PM.add(createAlphaCodeEmitterPass(*this, MCE)); if (DumpAsm) @@ -103,7 +104,8 @@ bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, return false; } bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, - unsigned OptLevel, bool DumpAsm, + CodeGenOpt::Level OptLevel, + bool DumpAsm, MachineCodeEmitter &MCE) { return addCodeEmitter(PM, OptLevel, DumpAsm, MCE); } diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h index 309c2e8877..8dd07db062 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.h +++ b/lib/Target/Alpha/AlphaTargetMachine.h @@ -58,14 +58,17 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE); + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + bool DumpAsm, + MachineCodeEmitter &MCE); }; } // end namespace llvm diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 292a380595..0d200c5a1d 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -37,7 +37,8 @@ namespace { /// explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(o, tm, T, OL, V) {} virtual const char *getPassName() const { @@ -68,7 +69,7 @@ namespace { /// FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o, TargetMachine &tm, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool verbose) { return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 0a8e9df523..5b35580a7d 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -3587,7 +3587,7 @@ void CWriter::visitExtractValueInst(ExtractValueInst &EVI) { bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o, CodeGenFileType FileType, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { if (FileType != TargetMachine::AssemblyFile) return true; PM.add(createGCLoweringPass()); diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h index a851486a20..8b262455ad 100644 --- a/lib/Target/CBackend/CTargetMachine.h +++ b/lib/Target/CBackend/CTargetMachine.h @@ -28,7 +28,7 @@ struct CTargetMachine : public TargetMachine { virtual bool WantsWholeFile() const { return true; } virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out, CodeGenFileType FileType, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); // This class always works, but must be requested explicitly on // llc command line. diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 6e77c87e6f..15cacd146a 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -49,7 +49,8 @@ namespace { std::set<std::string> FnStubs, GVStubs; public: explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) : + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { @@ -288,8 +289,9 @@ namespace { DwarfWriter *DW; MachineModuleInfo *MMI; public: - LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) + explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM, + const TargetAsmInfo *T, CodeGenOpt::Level F, + bool V) : SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {} virtual const char *getPassName() const { @@ -615,6 +617,7 @@ bool LinuxAsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o, SPUTargetMachine &tm, - unsigned OptLevel, bool verbose) { + CodeGenOpt::Level OptLevel, + bool verbose) { return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/CellSPU/SPU.h b/lib/Target/CellSPU/SPU.h index 5c62bc3a42..77a062e0e2 100644 --- a/lib/Target/CellSPU/SPU.h +++ b/lib/Target/CellSPU/SPU.h @@ -16,6 +16,7 @@ #define LLVM_TARGET_IBMCELLSPU_H #include "llvm/Support/DataTypes.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { class SPUTargetMachine; @@ -25,7 +26,8 @@ namespace llvm { FunctionPass *createSPUISelDag(SPUTargetMachine &TM); FunctionPass *createSPUAsmPrinterPass(raw_ostream &o, SPUTargetMachine &tm, - unsigned OptLevel, bool verbose); + CodeGenOpt::Level OptLevel, + bool verbose); /*--== Utility functions/predicates/etc used all over the place: --==*/ //! Predicate test for a signed 10-bit value diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index c8cf3643f5..7fa902243c 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -81,7 +81,8 @@ SPUTargetMachine::SPUTargetMachine(const Module &M, const std::string &FS) //===----------------------------------------------------------------------===// bool -SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) +SPUTargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // Install an instruction selector. PM.add(createSPUISelDag(*this)); @@ -89,7 +90,7 @@ SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) } bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose)); diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index e959e9187b..cd39203338 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -83,8 +83,10 @@ public: } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index 3d6362145e..849284e8d8 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -1995,7 +1995,7 @@ char CppWriter::ID = 0; bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o, CodeGenFileType FileType, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { if (FileType != TargetMachine::AssemblyFile) return true; PM.add(new CppWriter(o)); return false; diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h index 90b8268888..db4bc0e722 100644 --- a/lib/Target/CppBackend/CPPTargetMachine.h +++ b/lib/Target/CppBackend/CPPTargetMachine.h @@ -30,7 +30,7 @@ struct CPPTargetMachine : public TargetMachine { virtual bool WantsWholeFile() const { return true; } virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out, CodeGenFileType FileType, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); // This class always works, but shouldn't be the default in most cases. static unsigned getModuleMatchQuality(const Module &M) { return 1; } diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp index 5fd8811285..9cdcd73c63 100644 --- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Support/Mangler.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/Statistic.h" @@ -38,7 +37,8 @@ namespace { std::set<std::string> ExternalFunctionNames, ExternalObjectNames; public: explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { @@ -370,7 +370,7 @@ bool IA64AsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o, IA64TargetMachine &tm, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool verbose) { return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/IA64/IA64.h b/lib/Target/IA64/IA64.h index 46c26f0a5a..ec8e3d6d74 100644 --- a/lib/Target/IA64/IA64.h +++ b/lib/Target/IA64/IA64.h @@ -14,6 +14,8 @@ #ifndef TARGET_IA64_H #define TARGET_IA64_H +#include "llvm/Target/TargetMachine.h" + namespace llvm { class IA64TargetMachine; @@ -37,7 +39,8 @@ FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM); /// FunctionPass *createIA64CodePrinterPass(raw_ostream &o, IA64TargetMachine &tm, - unsigned OptLevel, bool verbose); + CodeGenOpt::Level OptLevel, + bool verbose); } // End llvm namespace diff --git a/lib/Target/IA64/IA64TargetMachine.cpp b/lib/Target/IA64/IA64TargetMachine.cpp index c472657c6e..878a00a445 100644 --- a/lib/Target/IA64/IA64TargetMachine.cpp +++ b/lib/Target/IA64/IA64TargetMachine.cpp @@ -72,18 +72,20 @@ IA64TargetMachine::IA64TargetMachine(const Module &M, const std::string &FS) // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){ +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel){ PM.add(createIA64DAGToDAGInstructionSelector(*this)); return false; } -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // Make sure everything is bundled happily PM.add(createIA64BundlingPass(*this)); return true; } bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose)); diff --git a/lib/Target/IA64/IA64TargetMachine.h b/lib/Target/IA64/IA64TargetMachine.h index 1fbba02da3..29d625ce67 100644 --- a/lib/Target/IA64/IA64TargetMachine.h +++ b/lib/Target/IA64/IA64TargetMachine.h @@ -51,9 +51,10 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); }; } // End llvm namespace diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index 8d9a1ea7ed..e5a1203d92 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -36,7 +36,7 @@ namespace { virtual bool WantsWholeFile() const { return true; } virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out, CodeGenFileType FileType, - unsigned OptLevel); + CodeGenOpt::Level OptLevel); // This class always works, but shouldn't be the default in most cases. static unsigned getModuleMatchQuality(const Module &M) { return 1; } @@ -1664,7 +1664,7 @@ void MSILWriter::printExternals() { bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o, CodeGenFileType FileType, - unsigned OptLevel) + CodeGenOpt::Level OptLevel) { if (FileType != TargetMachine::AssemblyFile) return true; MSILWriter* Writer = new MSILWriter(o); diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index 6692f2e40a..fd2ae51b97 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -50,7 +50,8 @@ namespace { const MipsSubtarget *Subtarget; public: explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V) { Subtarget = &TM.getSubtarget<MipsSubtarget>(); } @@ -91,7 +92,8 @@ namespace { /// regardless of whether the function is in SSA form. FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o, MipsTargetMachine &tm, - unsigned OptLevel, bool verbose) { + CodeGenOpt::Level OptLevel, + bool verbose) { return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h index abcb9c44fa..0accb4e347 100644 --- a/lib/Target/Mips/Mips.h +++ b/lib/Target/Mips/Mips.h @@ -15,6 +15,8 @@ #ifndef TARGET_MIPS_H #define TARGET_MIPS_H +#include "llvm/Target/TargetMachine.h" + namespace llvm { class MipsTargetMachine; class FunctionPass; @@ -25,7 +27,8 @@ namespace llvm { FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM); FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, MipsTargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); } // end namespace llvm; // Defines symbolic names for Mips registers. This defines a mapping from diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 69a480deab..ef524e3ecd 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -105,7 +105,7 @@ getModuleMatchQuality(const Module &M) // Install an instruction selector pass using // the ISelDag to gen Mips code. bool MipsTargetMachine:: -addInstSelector(PassManagerBase &PM, unsigned OptLevel) +addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { PM.add(createMipsISelDag(*this)); return false; @@ -115,7 +115,7 @@ addInstSelector(PassManagerBase &PM, unsigned OptLevel) // machine code is emitted. return true if -print-machineinstrs should // print out the code after the passes. bool MipsTargetMachine:: -addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) +addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { PM.add(createMipsDelaySlotFillerPass(*this)); return true; @@ -124,7 +124,7 @@ addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) // Implements the AssemblyEmitter for the target. Must return // true if AssemblyEmitter is supported bool MipsTargetMachine:: -addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, +addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { // Output assembly language. diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index b5dc058e9e..a9e1df27ae 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -57,9 +57,12 @@ namespace llvm { static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/lib/Target/PIC16/PIC16.h b/lib/Target/PIC16/PIC16.h index 695fe84aca..42bd7bc8e1 100644 --- a/lib/Target/PIC16/PIC16.h +++ b/lib/Target/PIC16/PIC16.h @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_PIC16_H #define LLVM_TARGET_PIC16_H +#include "llvm/Target/TargetMachine.h" #include <iosfwd> #include <cassert> @@ -75,7 +76,8 @@ namespace PIC16CC { FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM); FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, PIC16TargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); } // end namespace llvm; // Defines symbolic names for PIC16 registers. This defines a mapping from diff --git a/lib/Target/PIC16/PIC16AsmPrinter.cpp b/lib/Target/PIC16/PIC16AsmPrinter.cpp index a10fcd40b0..510e105ebd 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/PIC16AsmPrinter.cpp @@ -161,7 +161,7 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) { /// FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o, PIC16TargetMachine &tm, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool verbose) { return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/PIC16/PIC16AsmPrinter.h b/lib/Target/PIC16/PIC16AsmPrinter.h index 67eca1f590..227de7074b 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.h +++ b/lib/Target/PIC16/PIC16AsmPrinter.h @@ -25,7 +25,8 @@ namespace llvm { struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter { explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V) { CurBank = ""; FunctionLabelBegin = '@'; diff --git a/lib/Target/PIC16/PIC16TargetMachine.cpp b/lib/Target/PIC16/PIC16TargetMachine.cpp index adc2120a40..9c52ee54f2 100644 --- a/lib/Target/PIC16/PIC16TargetMachine.cpp +++ b/lib/Target/PIC16/PIC16TargetMachine.cpp @@ -56,15 +56,15 @@ const TargetAsmInfo *PIC16TargetMachine::createTargetAsmInfo() const { } bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { // Install an instruction selector. PM.add(createPIC16ISelDag(*this)); return false; } bool PIC16TargetMachine:: -addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, - raw_ostream &Out) { +addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, + bool Verbose, raw_ostream &Out) { // Output assembly language. PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose)); return false; diff --git a/lib/Target/PIC16/PIC16TargetMachine.h b/lib/Target/PIC16/PIC16TargetMachine.h index b6b5d31848..d960459265 100644 --- a/lib/Target/PIC16/PIC16TargetMachine.h +++ b/lib/Target/PIC16/PIC16TargetMachine.h @@ -57,8 +57,10 @@ public: return const_cast<PIC16TargetLowering*>(&TLInfo); } - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); }; // PIC16TargetMachine. diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index c690982751..96c86655d9 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -55,7 +55,8 @@ namespace { const PPCSubtarget &Subtarget; public: explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V), Subtarget(TM.getSubtarget<PPCSubtarget>()) {} @@ -298,7 +299,8 @@ namespace { MachineModuleInfo *MMI; public: explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {} virtual const char *getPassName() const { @@ -327,7 +329,8 @@ namespace { raw_ostream &OS; public: explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {} virtual const char *getPassName() const { @@ -1176,7 +1179,8 @@ bool PPCDarwinAsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o, PPCTargetMachine &tm, - unsigned OptLevel, bool verbose) { + CodeGenOpt::Level OptLevel, + bool verbose) { const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>(); if (Subtarget->isDarwin()) { diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index f5507c29be..78c970eab4 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -18,6 +18,8 @@ // GCC #defines PPC on Linux but we use it as our namespace name #undef PPC +#include "llvm/Target/TargetMachine.h" + namespace llvm { class PPCTargetMachine; class FunctionPass; @@ -28,7 +30,7 @@ FunctionPass *createPPCBranchSelectionPass(); FunctionPass *createPPCISelDag(PPCTargetMachine &TM); FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS, PPCTargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, bool Verbose); FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM, MachineCodeEmitter &MCE); } // end namespace llvm; diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 3e1dc3253b..bb17ea93fc 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -129,21 +129,22 @@ PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS) // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // Install an instruction selector. PM.add(createPPCISelDag(*this)); return false; } -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { - +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // Must run branch selection immediately preceding the asm printer. PM.add(createPPCBranchSelectionPass()); return false; } bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); @@ -153,7 +154,8 @@ bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, return false; } -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. // FIXME: This should be moved to TargetJITInfo!! @@ -184,7 +186,8 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, return false; } -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // Machine code emitter pass for PowerPC. PM.add(createPPCCodeEmitterPass(*this, MCE)); diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 2f839fb07b..efdf918d79 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -46,7 +46,8 @@ protected: // set this functions to ctor pointer at startup time if they are linked in. typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, PPCTargetMachine &tm, - unsigned OptLevel, bool verbose); + CodeGenOpt::Level OptLevel, + bool verbose); static AsmPrinterCtorFn AsmPrinterCtor; public: @@ -76,13 +77,15 @@ public: } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); virtual bool getEnableTailMergeDefault() const; }; diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index ab1868425c..115f9b05d2 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -49,7 +49,8 @@ namespace { ValueMapTy NumberForBB; public: explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { @@ -82,7 +83,7 @@ namespace { /// FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o, TargetMachine &tm, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool verbose) { return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 74b2e47614..bb03f30f2d 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -15,17 +15,18 @@ #ifndef TARGET_SPARC_H #define TARGET_SPARC_H +#include "llvm/Target/TargetMachine.h" #include <cassert> namespace llvm { class FunctionPass; - class TargetMachine; class SparcTargetMachine; class raw_ostream; FunctionPass *createSparcISelDag(SparcTargetMachine &TM); FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM); FunctionPass *createSparcFPMoverPass(TargetMachine &TM); } // end namespace llvm; diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index cabfce118a..eda0309241 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -69,7 +69,7 @@ unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) { } bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { PM.add(createSparcISelDag(*this)); return false; } @@ -77,14 +77,15 @@ bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, /// addPreEmitPass - This pass may be implemented by targets that want to run /// passes immediately before machine code is emitted. This should return /// true if -print-machineinstrs should print out the code after the passes. -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){ +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel){ PM.add(createSparcFPMoverPass(*this)); PM.add(createSparcDelaySlotFillerPass(*this)); return true; } bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { // Output assembly language. diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 927cbb5fa1..40b44f2fb3 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -51,9 +51,10 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h index ecb0f4db74..1e8b3ad919 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h @@ -34,7 +34,8 @@ class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter { const X86Subtarget *Subtarget; public: explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) { Subtarget = &TM.getSubtarget<X86Subtarget>(); } diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp index 85c5471277..c874849dc1 100644 --- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp @@ -25,7 +25,8 @@ using namespace llvm; /// FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o, X86TargetMachine &tm, - unsigned OptLevel, bool verbose) { + CodeGenOpt::Level OptLevel, + bool verbose) { const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>(); if (Subtarget->isFlavorIntel()) { diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h index 054cd9c70f..9520d982f6 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h @@ -26,7 +26,8 @@ namespace llvm { struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter { explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index 9dad017dd3..a9ac859e77 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -15,6 +15,8 @@ #ifndef TARGET_X86_H #define TARGET_X86_H +#include "llvm/Target/TargetMachine.h" + namespace llvm { class X86TargetMachine; @@ -25,7 +27,7 @@ class raw_ostream; /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize); +FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel); /// createX86FloatingPointStackifierPass - This function returns a pass which /// converts floating point register references and pseudo instructions into @@ -44,7 +46,8 @@ FunctionPass *createX87FPRegKillInserterPass(); /// FunctionPass *createX86CodePrinterPass(raw_ostream &o, X86TargetMachine &tm, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 7da43e97dc..ceac594bdb 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -134,7 +134,7 @@ namespace { bool OptForSize; public: - explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel) + explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) : SelectionDAGISel(tm, OptLevel), TM(tm), X86Lowering(*TM.getTargetLowering()), Subtarget(&TM.getSubtarget<X86Subtarget>()), @@ -306,7 +306,7 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const { - if (OptLevel == 0) return false; + if (OptLevel == CodeGenOpt::None) return false; if (U == Root) switch (U->getOpcode()) { @@ -714,7 +714,7 @@ void X86DAGToDAGISel::InstructionSelect() { OptForSize = F->hasFnAttr(Attribute::OptimizeForSize); DEBUG(BB->dump()); - if (OptLevel != 0) + if (OptLevel != CodeGenOpt::None) PreprocessForRMW(); // FIXME: This should only happen when not compiled with -O0. @@ -1744,6 +1744,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) { +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, + llvm::CodeGenOpt::Level OptLevel) { return new X86DAGToDAGISel(TM, OptLevel); } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index df086e8cea..761d098b5e 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -180,7 +180,8 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { +bool X86TargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // Install an instruction selector. PM.add(createX86ISelDag(*this, OptLevel)); @@ -194,20 +195,22 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { return false; } -bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) { +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { // Calculate and set max stack object alignment early, so we can decide // whether we will need stack realignment (and thus FP). PM.add(createX86MaxStackAlignmentCalculatorPass()); return false; // -print-machineinstr shouldn't print after this. } -bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) { +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { PM.add(createX86FloatingPointStackifierPass()); return true; // -print-machineinstr should print after this. } bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); @@ -216,7 +219,8 @@ bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, return false; } -bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! // On Darwin, do not override 64-bit setting made in X86TargetMachine(). @@ -245,7 +249,8 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, } bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, - unsigned OptLevel, bool DumpAsm, + CodeGenOpt::Level OptLevel, + bool DumpAsm, MachineCodeEmitter &MCE) { PM.add(createX86CodeEmitterPass(*this, MCE)); if (DumpAsm) { diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 4b4e26f600..c25fc1de04 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -45,7 +45,8 @@ protected: // set this functions to ctor pointer at startup time if they are linked in. typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, X86TargetMachine &tm, - unsigned OptLevel, bool verbose); + CodeGenOpt::Level OptLevel, + bool verbose); static AsmPrinterCtorFn AsmPrinterCtor; public: @@ -74,14 +75,16 @@ public: } // Set up the pass pipeline. - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel); - virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index 1c99d887b0..5722b873e1 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -15,6 +15,8 @@ #ifndef TARGET_XCORE_H #define TARGET_XCORE_H +#include "llvm/Target/TargetMachine.h" + namespace llvm { class FunctionPass; class TargetMachine; @@ -24,7 +26,8 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM); FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS, XCoreTargetMachine &TM, - unsigned OptLevel, bool Verbose); + CodeGenOpt::Level OptLevel, + bool Verbose); } // end namespace llvm; // Defines symbolic names for XCore registers. This defines a mapping from diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index accc35afbe..45b3c37aeb 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -57,8 +57,9 @@ namespace { DwarfWriter *DW; const XCoreSubtarget &Subtarget; public: - XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM, - const TargetAsmInfo *T, unsigned OL, bool V) + explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM, + const TargetAsmInfo *T, CodeGenOpt::Level OL, + bool V) : AsmPrinter(O, TM, T, OL, V), DW(0), Subtarget(*TM.getSubtargetImpl()) {} @@ -105,7 +106,7 @@ namespace { /// FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o, XCoreTargetMachine &tm, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool verbose) { return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index bb0ba775a2..5437c574a8 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -56,13 +56,13 @@ unsigned XCoreTargetMachine::getModuleMatchQuality(const Module &M) { } bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, - unsigned OptLevel) { + CodeGenOpt::Level OptLevel) { PM.add(createXCoreISelDag(*this)); return false; } bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, - unsigned OptLevel, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out) { // Output assembly language. diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index e57e672fad..2385aedc90 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -52,8 +52,9 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp index eff32270e7..cf58384378 100644 --- a/tools/llc/llc.cpp +++ b/tools/llc/llc.cpp @@ -56,12 +56,12 @@ OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename")); static cl::opt<bool> Force("f", cl::desc("Overwrite output files")); // Determine optimization level. Level -O0 is equivalent to "fast" code gen. -static cl::opt<unsigned> +static cl::opt<char> OptLevel("O", - cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"), + cl::desc("Optimization level. Similar to llvm-gcc -O."), cl::Prefix, cl::ZeroOrMore, - cl::init(3)); + cl::init(' ')); static cl::opt<std::string> TargetTriple("mtriple", cl::desc("Override target triple for module")); @@ -253,6 +253,19 @@ int main(int argc, char **argv) { raw_ostream *Out = GetOutputStream(argv[0]); if (Out == 0) return 1; + CodeGenOpt::Level OLvl = CodeGenOpt::Aggressive; + + switch (OptLevel) { + default: + case ' ': break; + case '0': OLvl = CodeGenOpt::None; break; + case '1': OLvl = CodeGenOpt::One; break; + case '2': OLvl = CodeGenOpt::Two; break; + case 's': OLvl = CodeGenOpt::Size; break; + case '3': OLvl = CodeGenOpt::Aggressive; break; + case '4': OLvl = CodeGenOpt::LTO; break; + } + // If this target requires addPassesToEmitWholeFile, do it now. This is // used by strange things like the C backend. if (Target.WantsWholeFile()) { @@ -262,7 +275,7 @@ int main(int argc, char **argv) { PM.add(createVerifierPass()); // Ask the target to add backend passes as necessary. - if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) { + if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OLvl)) { std::cerr << argv[0] << ": target does not support generation of this" << " file type!\n"; if (Out != &outs()) delete Out; @@ -288,7 +301,7 @@ int main(int argc, char **argv) { // Override default to generate verbose assembly. Target.setAsmVerbosityDefault(true); - switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) { + switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OLvl)) { default: assert(0 && "Invalid file model!"); return 1; @@ -309,7 +322,7 @@ int main(int argc, char **argv) { break; } - if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) { + if (Target.addPassesToEmitFileFinish(Passes, MCE, OLvl)) { std::cerr << argv[0] << ": target does not support generation of this" << " file type!\n"; if (Out != &outs()) delete Out; diff --git a/tools/lli/lli.cpp b/tools/lli/lli.cpp index d62d332098..812e52c8a9 100644 --- a/tools/lli/lli.cpp +++ b/tools/lli/lli.cpp @@ -122,7 +122,9 @@ int main(int argc, char **argv, char * const *envp) { if (!TargetTriple.empty()) Mod->setTargetTriple(TargetTriple); - EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg, Fast); + EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg, + Fast ? + CodeGenOpt::None : CodeGenOpt::Aggressive); if (!EE && !ErrorMsg.empty()) { std::cerr << argv[0] << ":error creating EE: " << ErrorMsg << "\n"; exit(1); diff --git a/tools/lto/LTOCodeGenerator.cpp b/tools/lto/LTOCodeGenerator.cpp index af8ad962cc..66b56b174c 100644 --- a/tools/lto/LTOCodeGenerator.cpp +++ b/tools/lto/LTOCodeGenerator.cpp @@ -442,7 +442,8 @@ bool LTOCodeGenerator::generateAssemblyCode(raw_ostream& out, MachineCodeEmitter* mce = NULL; switch (_target->addPassesToEmitFile(*codeGenPasses, out, - TargetMachine::AssemblyFile, 3)) { + TargetMachine::AssemblyFile, + CodeGenOpt::Default)) { case FileModel::MachOFile: mce = AddMachOWriter(*codeGenPasses, out, *_target); break; @@ -457,7 +458,8 @@ bool LTOCodeGenerator::generateAssemblyCode(raw_ostream& out, return true; } - if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) { + if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, + CodeGenOpt::Default)) { errMsg = "target does not support generation of this file type"; return true; } diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 6bcc52af8a..cfe1e5d589 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -650,7 +650,7 @@ void AsmWriterEmitter::run(std::ostream &O) { O << "\";\n\n"; O << " if (TAI->doesSupportDebugInformation() &&\n" - << " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n" + << " DW->ShouldEmitDwarfDebug() && OptLevel != CodeGenOpt::None) {\n" << " DebugLoc CurDL = MI->getDebugLoc();\n\n" << " if (!CurDL.isUnknown()) {\n" << " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n" diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index b5d334c40d..e3858cc3fc 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -465,7 +465,7 @@ public: NumInputRootOps = N->getNumChildren(); if (DisablePatternForFastISel(N, CGP)) - emitCheck("OptLevel != 0"); + emitCheck("OptLevel != CodeGenOpt::None"); emitCheck(PredicateCheck); } |