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| author | Jim Grosbach <grosbach@apple.com> | 2010-11-10 23:12:48 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-11-10 23:12:48 +0000 |
| commit | 866aa394ca72ca015e65fff55043bc1120b3b58d (patch) | |
| tree | 44fe6470b433ffb093efa2008170c2356c07ae63 | |
| parent | 2365f08c7dfd039ef325d8cb4621b40fc5bd605f (diff) | |
Fix ARM encoding of LDM+Return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 7 |
2 files changed, 10 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 7add36b1ac..ddf0c82e55 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -941,9 +941,11 @@ class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { bits<16> dsts; - let Inst{20} = 1; // L bit - let Inst{22} = 0; // S bit + bits<4> Rn; let Inst{27-25} = 0b100; + let Inst{22} = 0; // S bit + let Inst{20} = 1; // L bit + let Inst{19-16} = Rn; let Inst{15-0} = dsts; } class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 64a3dc73ce..9865ee5e54 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1183,7 +1183,12 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, reglist:$dsts, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, "ldm${mode}${p}\t$Rn!, $dsts", - "$Rn = $wb", []>; + "$Rn = $wb", []> { + bits<4> p; + let Inst{31-28} = p; + let Inst{24-23} = 0b01; + let Inst{21} = 1; +} // On non-Darwin platforms R9 is callee-saved. let isCall = 1, |