diff options
author | Chris Lattner <sabre@nondot.org> | 2005-10-26 18:01:11 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2005-10-26 18:01:11 +0000 |
commit | 85fd97dc8810ac16197594304f9f985a13466d19 (patch) | |
tree | 32c83392bd0c89ecfc6c2118ac32e79f28d4f233 | |
parent | ff2fcee846addcb64b6fad0efa339949d26b7390 (diff) |
Fix an assert compiling MallocBench/gs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24017 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 4deff28bf0..30525cffd0 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -217,7 +217,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, ResVT, - DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV); + DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); } SDOperand Cmp; |