implement LDRB, LDRSB, LDRH and LDRSH

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30976 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 53 insertions, 0 deletions

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 6582a5b264..23b2155c85 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -113,6 +113,22 @@ def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
                      "ldr $dst, $addr",
                      [(set IntRegs:$dst, (load iaddr:$addr))]>;
 
+def LDRB    : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+                       "ldrb $dst, $addr",
+                       [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
+
+def LDRSB   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+                       "ldrsb $dst, $addr",
+                       [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
+
+def LDRH    : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+                       "ldrh $dst, $addr",
+                       [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
+
+def LDRSH   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+                       "ldrsh $dst, $addr",
+                       [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
+
 def str  : InstARM<(ops IntRegs:$src, memri:$addr),
                     "str $src, $addr",
                     [(store IntRegs:$src, iaddr:$addr)]>;
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index 768a2e6f3e..9e846565c8 100644
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -51,3 +51,7 @@ Only needs 8 bytes of stack space. We currently allocate 16.
 should try to declare smull and umull as returning two values.
 
 ----------------------------------------------------------
+
+Implement addressing modes 2 (ldrb) and 3 (ldrsb)
+
+----------------------------------------------------------
diff --git a/test/CodeGen/ARM/load.ll b/test/CodeGen/ARM/load.ll
new file mode 100644
index 0000000000..603a8b2780
--- /dev/null
+++ b/test/CodeGen/ARM/load.ll
@@ -0,0 +1,33 @@
+; RUN: llvm-as < %s | llc -march=arm &&
+; RUN: llvm-as < %s | llc -march=arm | grep ldrsb &&
+; RUN: llvm-as < %s | llc -march=arm | grep ldrb &&
+; RUN: llvm-as < %s | llc -march=arm | grep ldrsh &&
+; RUN: llvm-as < %s | llc -march=arm | grep ldrh
+
+int %f1(sbyte* %p) {
+entry:
+	%tmp = load sbyte* %p		; <sbyte> [#uses=1]
+	%tmp = cast sbyte %tmp to int		; <int> [#uses=1]
+	ret int %tmp
+}
+
+int %f2(ubyte* %p) {
+entry:
+	%tmp = load ubyte* %p		; <sbyte> [#uses=1]
+	%tmp = cast ubyte %tmp to int		; <int> [#uses=1]
+	ret int %tmp
+}
+
+int %f3(short* %p) {
+entry:
+	%tmp = load short* %p		; <sbyte> [#uses=1]
+	%tmp = cast short %tmp to int		; <int> [#uses=1]
+	ret int %tmp
+}
+
+int %f4(ushort* %p) {
+entry:
+	%tmp = load ushort* %p		; <sbyte> [#uses=1]
+	%tmp = cast ushort %tmp to int		; <int> [#uses=1]
+	ret int %tmp
+}