Print mflr using the asmwriter generator

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15749 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 33 insertions, 2 deletions

diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
index afe7c35470..a857f3afeb 100644
--- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
@@ -27,6 +27,7 @@
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "Support/CommandLine.h"
@@ -82,6 +83,17 @@ namespace {
     void printMachineInstruction(const MachineInstr *MI);
     void printOp(const MachineOperand &MO, bool LoadAddrOp = false);
     void printImmOp(const MachineOperand &MO, unsigned ArgType);
+
+    void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+      const MachineOperand &MO = MI->getOperand(OpNo);
+      if (MO.getType() == MachineOperand::MO_MachineRegister) {
+        assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
+        O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name);
+      } else {
+        printOp(MO);
+      }
+    }
+
     void printConstantPool(MachineConstantPool *MCP);
     bool runOnMachineFunction(MachineFunction &F);    
     bool doInitialization(Module &M);
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index afe7c35470..a857f3afeb 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -27,6 +27,7 @@
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "Support/CommandLine.h"
@@ -82,6 +83,17 @@ namespace {
     void printMachineInstruction(const MachineInstr *MI);
     void printOp(const MachineOperand &MO, bool LoadAddrOp = false);
     void printImmOp(const MachineOperand &MO, unsigned ArgType);
+
+    void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+      const MachineOperand &MO = MI->getOperand(OpNo);
+      if (MO.getType() == MachineOperand::MO_MachineRegister) {
+        assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
+        O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name);
+      } else {
+        printOp(MO);
+      }
+    }
+
     void printConstantPool(MachineConstantPool *MCP);
     bool runOnMachineFunction(MachineFunction &F);    
     bool doInitialization(Module &M);
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index f21320f5d8..a334249aba 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -15,7 +15,13 @@
 include "PowerPCInstrFormats.td"
 
 let isTerminator = 1, isReturn = 1 in
-	def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
+  def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
+
+class II<dag OL, string asmstr> {
+  dag OperandList = OL;
+  string AsmString = asmstr;
+}
+
 
 // Pseudo-instructions:
 def PHI : Pseudo<"PHI">;          // PHI node...
@@ -121,7 +127,8 @@ def LFSX : XForm_25<"lfsx", 31, 535, 0, 0>;
 def LFD : DForm_8<"lfd", 50, 0, 0>;
 def LFDX : XForm_25<"lfdx", 31, 599, 0, 0>;
 def MFCR : XForm_5<"mfcr", 31, 19, 0, 0>;
-def MFLR : XFXForm_1_ext<"mflr", 31, 399, 8, 0, 0>;
+def MFLR : XFXForm_1_ext<"", 31, 399, 8, 0, 0>,
+                      II<(ops GPRC:$reg), "mflr $reg">;
 def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
 def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
 def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;