diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-02-25 21:03:02 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-02-25 21:03:02 +0000 |
| commit | 757df0282652a9623891baf00d83e03964bb38b1 (patch) | |
| tree | d5de3730cdb7189cda39f207e6678debf50e3af8 | |
| parent | e07c2aa67cad10d6793c649639fece58dcea6d20 (diff) | |
SparcV8 regs are really 32-bit, not 64! Thanks, Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11835 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Sparc/SparcV8Reg.td | 2 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8Reg.td | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Sparc/SparcV8Reg.td b/lib/Target/Sparc/SparcV8Reg.td index 3813d25261..f58d06adf7 100644 --- a/lib/Target/Sparc/SparcV8Reg.td +++ b/lib/Target/Sparc/SparcV8Reg.td @@ -36,7 +36,7 @@ let Namespace = "SparcV8" in { // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7, +def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O6, O7, L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, I6, I7]>; diff --git a/lib/Target/SparcV8/SparcV8Reg.td b/lib/Target/SparcV8/SparcV8Reg.td index 3813d25261..f58d06adf7 100644 --- a/lib/Target/SparcV8/SparcV8Reg.td +++ b/lib/Target/SparcV8/SparcV8Reg.td @@ -36,7 +36,7 @@ let Namespace = "SparcV8" in { // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7, +def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O6, O7, L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, I6, I7]>; |