rename TargetInstrDescriptor -> TargetInstrDesc.

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8

42 files changed, 234 insertions, 233 deletions

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 5450e839db..72463f98d8 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -20,7 +20,7 @@
 
 namespace llvm {
 
-class TargetInstrDescriptor;
+class TargetInstrDesc;
 
 template <typename T> struct ilist_traits;
 template <typename T> struct ilist;
@@ -29,7 +29,7 @@ template <typename T> struct ilist;
 /// MachineInstr - Representation of each machine instruction.
 ///
 class MachineInstr {
-  const TargetInstrDescriptor *TID;     // Instruction descriptor.
+  const TargetInstrDesc *TID;           // Instruction descriptor.
   unsigned short NumImplicitOps;        // Number of implicit operands (which
                                         // are determined at construction time).
 
@@ -54,14 +54,14 @@ public:
 
   /// MachineInstr ctor - This constructor create a MachineInstr and add the
   /// implicit operands.  It reserves space for number of operands specified by
-  /// TargetInstrDescriptor.
-  explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
+  /// TargetInstrDesc.
+  explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
 
   /// MachineInstr ctor - Work exactly the same as the ctor above, except that
   /// the MachineInstr is created and added to the end of the specified basic
   /// block.
   ///
-  MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
+  MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
 
   ~MachineInstr();
 
@@ -70,7 +70,7 @@ public:
   
   /// getDesc - Returns the target instruction descriptor of this
   /// MachineInstr.
-  const TargetInstrDescriptor *getDesc() const { return TID; }
+  const TargetInstrDesc &getDesc() const { return *TID; }
 
   /// getOpcode - Returns the opcode of this MachineInstr.
   ///
@@ -166,7 +166,7 @@ public:
   /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
   /// the current instruction with a new one.
   ///
-  void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
+  void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; }
 
   /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
   /// fewer operand than it started with.
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 91c4ad9ac1..97d6736ac0 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -22,7 +22,7 @@
 
 namespace llvm {
 
-class TargetInstrDescriptor;
+class TargetInstrDesc;
 
 class MachineInstrBuilder {
   MachineInstr *MI;
@@ -88,14 +88,14 @@ public:
 /// BuildMI - Builder interface.  Specify how to create the initial instruction
 /// itself.
 ///
-inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
+inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
   return MachineInstrBuilder(new MachineInstr(TID));
 }
 
 /// BuildMI - This version of the builder sets up the first operand as a
 /// destination virtual register.
 ///
-inline MachineInstrBuilder  BuildMI(const TargetInstrDescriptor &TID,
+inline MachineInstrBuilder  BuildMI(const TargetInstrDesc &TID,
                                     unsigned DestReg) {
   return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
 }
@@ -106,7 +106,7 @@ inline MachineInstrBuilder  BuildMI(const TargetInstrDescriptor &TID,
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
-                                   const TargetInstrDescriptor &TID,
+                                   const TargetInstrDesc &TID,
                                    unsigned DestReg) {
   MachineInstr *MI = new MachineInstr(TID);
   BB.insert(I, MI);
@@ -119,7 +119,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
-                                   const TargetInstrDescriptor &TID) {
+                                   const TargetInstrDesc &TID) {
   MachineInstr *MI = new MachineInstr(TID);
   BB.insert(I, MI);
   return MachineInstrBuilder(MI);
@@ -130,7 +130,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
 /// destination register.
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
-                                   const TargetInstrDescriptor &TID) {
+                                   const TargetInstrDesc &TID) {
   return BuildMI(*BB, BB->end(), TID);
 }
 
@@ -139,7 +139,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
 /// operand as a destination virtual register. 
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
-                                   const TargetInstrDescriptor &TID,
+                                   const TargetInstrDesc &TID,
                                    unsigned DestReg) {
   return BuildMI(*BB, BB->end(), TID, DestReg);
 }
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index a07d0e9482..37c0a9032a 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -31,7 +31,7 @@ namespace llvm {
   class SelectionDAG;
   class SelectionDAGISel;
   class TargetInstrInfo;
-  class TargetInstrDescriptor;
+  class TargetInstrDesc;
   class TargetMachine;
   class TargetRegisterClass;
 
@@ -335,7 +335,7 @@ namespace llvm {
                          DenseMap<SDOperand, unsigned> &VRBaseMap);
     
     void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
-                                const TargetInstrDescriptor &II,
+                                const TargetInstrDesc &II,
                                 DenseMap<SDOperand, unsigned> &VRBaseMap);
 
     void EmitSchedule();
@@ -353,7 +353,7 @@ namespace llvm {
                         DenseMap<SDOperand, unsigned> &VRBaseMap);
   
     void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
-                    const TargetInstrDescriptor *II,
+                    const TargetInstrDesc *II,
                     DenseMap<SDOperand, unsigned> &VRBaseMap);
   };
 
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 36ea5c3180..f2d38f4b87 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -82,10 +82,10 @@ public:
 // Machine Instruction Flags and Description
 //===----------------------------------------------------------------------===//
 
-/// TargetInstrDescriptor flags - These should be considered private to the
-/// implementation of the TargetInstrDescriptor class.  Clients should use the
-/// predicate methods on TargetInstrDescriptor, not use these directly.  These
-/// all correspond to bitfields in the TargetInstrDescriptor::Flags field.
+/// TargetInstrDesc flags - These should be considered private to the
+/// implementation of the TargetInstrDesc class.  Clients should use the
+/// predicate methods on TargetInstrDesc, not use these directly.  These
+/// all correspond to bitfields in the TargetInstrDesc::Flags field.
 namespace TID {
   enum {
     Variadic = 0,
@@ -111,12 +111,12 @@ namespace TID {
   };
 }
 
-/// TargetInstrDescriptor - Describe properties that are true of each
+/// TargetInstrDesc - Describe properties that are true of each
 /// instruction in the target description file.  This captures information about
 /// side effects, register use and many other things.  There is one instance of
 /// this struct for each target instruction class, and the MachineInstr class
 /// points to this struct directly to describe itself.
-class TargetInstrDescriptor {
+class TargetInstrDesc {
 public:
   unsigned short  Opcode;        // The opcode number.
   unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
@@ -147,6 +147,11 @@ public:
   /// dest operand. Returns -1 if there isn't one.
   int findTiedToSrcOperand(unsigned OpNum) const;
   
+  /// getOpcode - Return the opcode number for this descriptor.
+  unsigned getOpcode() const {
+    return Opcode;
+  }
+  
   /// getName - Return the name of the record in the .td file for this
   /// instruction, for example "ADD8ri".
   const char *getName() const {
@@ -421,14 +426,13 @@ public:
 /// TargetInstrInfo - Interface to description of machine instructions
 ///
 class TargetInstrInfo {
-  const TargetInstrDescriptor* desc;    // raw array to allow static init'n
-  unsigned NumOpcodes;                  // number of entries in the desc array
-  unsigned numRealOpCodes;              // number of non-dummy op codes
+  const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
+  unsigned NumOpcodes;                // Number of entries in the desc array
 
   TargetInstrInfo(const TargetInstrInfo &);  // DO NOT IMPLEMENT
   void operator=(const TargetInstrInfo &);   // DO NOT IMPLEMENT
 public:
-  TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
+  TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
   virtual ~TargetInstrInfo();
 
   // Invariant opcodes: All instruction sets have these as their low opcodes.
@@ -445,16 +449,16 @@ public:
   /// get - Return the machine instruction descriptor that corresponds to the
   /// specified instruction opcode.
   ///
-  const TargetInstrDescriptor& get(unsigned Opcode) const {
-    assert(Opcode < NumOpcodes);
-    return desc[Opcode];
+  const TargetInstrDesc &get(unsigned Opcode) const {
+    assert(Opcode < NumOpcodes && "Invalid opcode!");
+    return Descriptors[Opcode];
   }
 
   /// isTriviallyReMaterializable - Return true if the instruction is trivially
   /// rematerializable, meaning it has no side effects and requires no operands
   /// that aren't always available.
   bool isTriviallyReMaterializable(MachineInstr *MI) const {
-    return MI->getDesc()->isRematerializable() &&
+    return MI->getDesc().isRematerializable() &&
            isReallyTriviallyReMaterializable(MI);
   }
 
@@ -462,9 +466,9 @@ public:
   /// effects that are not captured by any operands of the instruction or other
   /// flags.
   bool hasUnmodelledSideEffects(MachineInstr *MI) const {
-    const TargetInstrDescriptor *TID = MI->getDesc();
-    if (TID->hasNoSideEffects()) return false;
-    if (!TID->hasConditionalSideEffects()) return true;
+    const TargetInstrDesc &TID = MI->getDesc();
+    if (TID.hasNoSideEffects()) return false;
+    if (!TID.hasConditionalSideEffects()) return true;
     return !isReallySideEffectFree(MI); // May have side effects
   }
 protected:
@@ -773,7 +777,7 @@ public:
 /// libcodegen, not in libtarget.
 class TargetInstrInfoImpl : public TargetInstrInfo {
 protected:
-  TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
+  TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
   : TargetInstrInfo(desc, NumOpcodes) {}
 public:
   virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 726a41536e..36c5d7f8db 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -24,7 +24,6 @@ class TargetAsmInfo;
 class TargetData;
 class TargetSubtarget;
 class TargetInstrInfo;
-class TargetInstrDescriptor;
 class TargetJITInfo;
 class TargetLowering;
 class TargetFrameInfo;
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp
index 8ab4d4bdf9..0ca10b3cec 100644
--- a/lib/CodeGen/BranchFolding.cpp
+++ b/lib/CodeGen/BranchFolding.cpp
@@ -349,10 +349,10 @@ static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
                                 MachineBasicBlock::iterator E) {
   unsigned Time = 0;
   for (; I != E; ++I) {
-    const TargetInstrDescriptor *TID = I->getDesc();
-    if (TID->isCall())
+    const TargetInstrDesc &TID = I->getDesc();
+    if (TID.isCall())
       Time += 10;
-    else if (TID->isSimpleLoad() || TID->mayStore())
+    else if (TID.isSimpleLoad() || TID.mayStore())
       Time += 2;
     else
       ++Time;
@@ -778,7 +778,7 @@ static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
 
   MachineInstr *MBB1I = --MBB1->end();
   MachineInstr *MBB2I = --MBB2->end();
-  return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
+  return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
 }
 
 /// OptimizeBlock - Analyze and optimize control flow related to the specified
@@ -958,7 +958,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
     // If this branch is the only thing in its block, see if we can forward
     // other blocks across it.
     if (CurTBB && CurCond.empty() && CurFBB == 0 && 
-        MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
+        MBB->begin()->getDesc().isBranch() && CurTBB != MBB) {
       // This block may contain just an unconditional branch.  Because there can
       // be 'non-branch terminators' in the block, try removing the branch and
       // then seeing if the block is empty.
diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp
index 36e3fed6bf..1064e59095 100644
--- a/lib/CodeGen/Collector.cpp
+++ b/lib/CodeGen/Collector.cpp
@@ -359,7 +359,7 @@ void MachineCodeAnalysis::FindSafePoints(MachineFunction &MF) {
                                  BBE = MF.end(); BBI != BBE; ++BBI)
     for (MachineBasicBlock::iterator MI = BBI->begin(),
                                      ME = BBI->end(); MI != ME; ++MI)
-      if (MI->getDesc()->isCall())
+      if (MI->getDesc().isCall())
         VisitCallPoint(*MI);
 }
 
diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp
index 0fb71760d1..c1091e9e7d 100644
--- a/lib/CodeGen/DwarfWriter.cpp
+++ b/lib/CodeGen/DwarfWriter.cpp
@@ -3153,7 +3153,7 @@ private:
       for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
            MI != E; ++MI) {
         if (MI->getOpcode() != TargetInstrInfo::LABEL) {
-          SawPotentiallyThrowing |= MI->getDesc()->isCall();
+          SawPotentiallyThrowing |= MI->getDesc().isCall();
           continue;
         }
 
diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp
index a98347b486..2b3bdc2c98 100644
--- a/lib/CodeGen/IfConversion.cpp
+++ b/lib/CodeGen/IfConversion.cpp
@@ -460,7 +460,7 @@ MachineBasicBlock::iterator firstNonBranchInst(MachineBasicBlock *BB,
   MachineBasicBlock::iterator I = BB->end();
   while (I != BB->begin()) {
     --I;
-    if (!I->getDesc()->isBranch())
+    if (!I->getDesc().isBranch())
       break;
   }
   return I;
@@ -548,12 +548,12 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
   bool SeenCondBr = false;
   for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
        I != E; ++I) {
-    const TargetInstrDescriptor *TID = I->getDesc();
-    if (TID->isNotDuplicable())
+    const TargetInstrDesc &TID = I->getDesc();
+    if (TID.isNotDuplicable())
       BBI.CannotBeCopied = true;
 
     bool isPredicated = TII->isPredicated(I);
-    bool isCondBr = BBI.IsBrAnalyzable && TID->isConditionalBranch();
+    bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch();
 
     if (!isCondBr) {
       if (!isPredicated)
@@ -590,7 +590,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
     if (TII->DefinesPredicate(I, PredDefs))
       BBI.ClobbersPred = true;
 
-    if (!TID->isPredicable()) {
+    if (!TID.isPredicable()) {
       BBI.IsUnpredicable = true;
       return;
     }
@@ -1132,10 +1132,10 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
                                         bool IgnoreBr) {
   for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
          E = FromBBI.BB->end(); I != E; ++I) {
-    const TargetInstrDescriptor *TID = I->getDesc();
+    const TargetInstrDesc &TID = I->getDesc();
     bool isPredicated = TII->isPredicated(I);
     // Do not copy the end of the block branches.
-    if (IgnoreBr && !isPredicated && TID->isBranch())
+    if (IgnoreBr && !isPredicated && TID.isBranch())
       break;
 
     MachineInstr *MI = I->clone();
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 3d0e23c51b..80d3547e4b 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -615,9 +615,9 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
     return false;
 
   isLoad = false;
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  if (TID->isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
-    isLoad = TID->isSimpleLoad();
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (TID.isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
+    isLoad = TID.isSimpleLoad();
     return true;
   }
 
@@ -679,9 +679,9 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
                                          SmallVector<unsigned, 2> &Ops,
                                          bool isSS, int Slot, unsigned Reg) {
   unsigned MRInfo = 0;
-  const TargetInstrDescriptor *TID = MI->getDesc();
+  const TargetInstrDesc &TID = MI->getDesc();
   // If it is an implicit def instruction, just delete it.
-  if (TID->isImplicitDef()) {
+  if (TID.isImplicitDef()) {
     RemoveMachineInstrFromMaps(MI);
     vrm.RemoveMachineInstrFromMaps(MI);
     MI->eraseFromParent();
@@ -699,7 +699,7 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
       MRInfo |= (unsigned)VirtRegMap::isMod;
     else {
       // Filter out two-address use operand(s).
-      if (TID->getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
+      if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
         MRInfo = VirtRegMap::isModRef;
         continue;
       }
@@ -1225,7 +1225,7 @@ addIntervalsForSpills(const LiveInterval &li,
     int LdSlot = 0;
     bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
     bool isLoad = isLoadSS ||
-      (DefIsReMat && (ReMatDefMI->getDesc()->isSimpleLoad()));
+      (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
     bool IsFirstRange = true;
     for (LiveInterval::Ranges::const_iterator
            I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
@@ -1307,7 +1307,7 @@ addIntervalsForSpills(const LiveInterval &li,
     int LdSlot = 0;
     bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
     bool isLoad = isLoadSS ||
-      (DefIsReMat && ReMatDefMI->getDesc()->isSimpleLoad());
+      (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
     rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
                                Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
                                CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
@@ -1422,7 +1422,7 @@ addIntervalsForSpills(const LiveInterval &li,
           int LdSlot = 0;
           bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
           // If the rematerializable def is a load, also try to fold it.
-          if (isLoadSS || ReMatDefMI->getDesc()->isSimpleLoad())
+          if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
             Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
                                           Ops, isLoadSS, LdSlot, VReg);
         }
@@ -1450,7 +1450,7 @@ addIntervalsForSpills(const LiveInterval &li,
         MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
         int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
         assert(UseIdx != -1);
-        if (LastUse->getDesc()->getOperandConstraint(UseIdx, TOI::TIED_TO) ==
+        if (LastUse->getDesc().getOperandConstraint(UseIdx, TOI::TIED_TO) ==
             -1) {
           LastUse->getOperand(UseIdx).setIsKill();
           vrm.addKillPoint(LI->reg, LastUseIdx);
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 1e692c5d73..4965b1b953 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -535,7 +535,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
 
     // Finally, if the last instruction in the block is a return, make sure to mark
     // it as using all of the live-out values in the function.
-    if (!MBB->empty() && MBB->back().getDesc()->isReturn()) {
+    if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
       MachineInstr *Ret = &MBB->back();
       for (MachineRegisterInfo::liveout_iterator
            I = MF->getRegInfo().liveout_begin(),
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index d2dcd382ed..a85239b834 100644
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -132,9 +132,9 @@ void ilist_traits<MachineInstr>::transferNodesFromList(
 
 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
   iterator I = end();
-  while (I != begin() && (--I)->getDesc()->isTerminator())
+  while (I != begin() && (--I)->getDesc().isTerminator())
     ; /*noop */
-  if (I != end() && !I->getDesc()->isTerminator()) ++I;
+  if (I != end() && !I->getDesc().isTerminator()) ++I;
   return I;
 }
 
@@ -261,7 +261,7 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
   MachineBasicBlock::iterator I = end();
   while (I != begin()) {
     --I;
-    if (!I->getDesc()->isTerminator()) break;
+    if (!I->getDesc().isTerminator()) break;
 
     // Scan the operands of this machine instruction, replacing any uses of Old
     // with New.
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index d040bd45da..72f5a4c142 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -248,9 +248,9 @@ void MachineInstr::addImplicitDefUseOperands() {
 
 /// MachineInstr ctor - This constructor create a MachineInstr and add the
 /// implicit operands. It reserves space for number of operands specified by
-/// TargetInstrDescriptor or the numOperands if it is not zero. (for
+/// TargetInstrDesc or the numOperands if it is not zero. (for
 /// instructions with variable number of operands).
-MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
+MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
   : TID(&tid), NumImplicitOps(0), Parent(0) {
   if (!NoImp && TID->getImplicitDefs())
     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
@@ -269,7 +269,7 @@ MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
 /// MachineInstr is created and added to the end of the specified basic block.
 ///
 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
-                           const TargetInstrDescriptor &tid)
+                           const TargetInstrDesc &tid)
   : TID(&tid), NumImplicitOps(0), Parent(0) {
   assert(MBB && "Cannot use inserting ctor with null basic block!");
   if (TID->ImplicitDefs)
@@ -288,7 +288,7 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB,
 /// MachineInstr ctor - Copies MachineInstr arg exactly
 ///
 MachineInstr::MachineInstr(const MachineInstr &MI) {
-  TID = MI.getDesc();
+  TID = &MI.getDesc();
   NumImplicitOps = MI.NumImplicitOps;
   Operands.reserve(MI.getNumOperands());
 
@@ -537,10 +537,10 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
 /// operand list that is used to represent the predicate. It returns -1 if
 /// none is found.
 int MachineInstr::findFirstPredOperandIdx() const {
-  const TargetInstrDescriptor *TID = getDesc();
-  if (TID->isPredicable()) {
+  const TargetInstrDesc &TID = getDesc();
+  if (TID.isPredicable()) {
     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-      if (TID->OpInfo[i].isPredicate())
+      if (TID.OpInfo[i].isPredicate())
         return i;
   }
 
@@ -550,14 +550,14 @@ int MachineInstr::findFirstPredOperandIdx() const {
 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
 /// to two addr elimination.
 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
-  const TargetInstrDescriptor *TID = getDesc();
+  const TargetInstrDesc &TID = getDesc();
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     const MachineOperand &MO1 = getOperand(i);
     if (MO1.isRegister() && MO1.is