diff options
| author | Dan Gohman <gohman@apple.com> | 2008-04-12 02:35:39 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-04-12 02:35:39 +0000 |
| commit | 6f836adafee88669273e9302e3344c4b9cef8a0d (patch) | |
| tree | 39ea81835a3c49c8acf003fa37c70099db54fa87 | |
| parent | 6795ebb663bc2a9d5fddbaa22a43521bddc882fe (diff) | |
Fix a bug that prevented x86-64 from using rep.movsq for
8-byte-aligned data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49571 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/byval2.ll | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1ab272781b..66384f921c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4621,7 +4621,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) { ValReg = X86::EAX; Val = (Val << 8) | Val; Val = (Val << 16) | Val; - if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned + if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned AVT = MVT::i64; ValReg = X86::RAX; Val = (Val << 32) | Val; @@ -4740,7 +4740,7 @@ SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain, break; case 0: // DWORD aligned AVT = MVT::i32; - if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned + if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned AVT = MVT::i64; break; default: // Byte aligned diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll index d017aa5fa3..f438160bda 100644 --- a/test/CodeGen/X86/byval2.ll +++ b/test/CodeGen/X86/byval2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2 +; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2 ; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2 %struct.s = type { i64, i64, i64 } |