diff options
| author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-11-10 21:21:36 +0000 |
|---|---|---|
| committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-11-10 21:21:36 +0000 |
| commit | 65480b75afbb856e91cf95d2a38bc784a2dc3d30 (patch) | |
| tree | 267dc75a42994ddc7f8bfeb090985b47c98f99ff | |
| parent | ae4bcd7566752af5a15a40026c39a92da3eadec4 (diff) | |
Changed code to ignore Phi Nodes in PhyRegAlloc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1253 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | 7 | ||||
| -rw-r--r-- | lib/CodeGen/RegAlloc/RegClass.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp | 7 | ||||
| -rw-r--r-- | lib/Target/SparcV9/RegAlloc/RegClass.cpp | 2 |
4 files changed, 16 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index 8e4530c15d..bc82565734 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -355,6 +355,11 @@ void PhyRegAlloc::updateMachineCode() MachineInstr *MInst = *MInstIterator; + // do not process Phis + if( (TM.getInstrInfo()).isPhi( MInst->getOpCode()) ) + continue; + + // if this machine instr is call, insert caller saving code if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) ) @@ -579,7 +584,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, } // if !DEF cerr << "\nFor Inst " << *MInst; - cerr << "\n - SPILLED LR:"; LR->printSet(); + cerr << " - SPILLED LR: "; LR->printSet(); cerr << "\n - Added Instructions:"; if( MIBef ) cerr << *MIBef; cerr << *AdIMid; diff --git a/lib/CodeGen/RegAlloc/RegClass.cpp b/lib/CodeGen/RegAlloc/RegClass.cpp index 1219147ab2..d0f1c44430 100644 --- a/lib/CodeGen/RegAlloc/RegClass.cpp +++ b/lib/CodeGen/RegAlloc/RegClass.cpp @@ -82,6 +82,8 @@ void RegClass::pushAllIGNodes() // now push NON-constrined ones, if any NeedMoreSpills = ! pushUnconstrainedIGNodes(); + cerr << "\nConstrained IG Node found !@!" << IGNodeSpill->getIndex(); + } while( NeedMoreSpills ); // repeat until we have pushed all } diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 8e4530c15d..bc82565734 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -355,6 +355,11 @@ void PhyRegAlloc::updateMachineCode() MachineInstr *MInst = *MInstIterator; + // do not process Phis + if( (TM.getInstrInfo()).isPhi( MInst->getOpCode()) ) + continue; + + // if this machine instr is call, insert caller saving code if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) ) @@ -579,7 +584,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, } // if !DEF cerr << "\nFor Inst " << *MInst; - cerr << "\n - SPILLED LR:"; LR->printSet(); + cerr << " - SPILLED LR: "; LR->printSet(); cerr << "\n - Added Instructions:"; if( MIBef ) cerr << *MIBef; cerr << *AdIMid; diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp index 1219147ab2..d0f1c44430 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp +++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp @@ -82,6 +82,8 @@ void RegClass::pushAllIGNodes() // now push NON-constrined ones, if any NeedMoreSpills = ! pushUnconstrainedIGNodes(); + cerr << "\nConstrained IG Node found !@!" << IGNodeSpill->getIndex(); + } while( NeedMoreSpills ); // repeat until we have pushed all } |