Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8

15 files changed, 68 insertions, 68 deletions

diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index 30561dc54c..12b022e0f9 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -508,9 +508,9 @@ public:
                                    const TargetRegisterClass *RC) const = 0;
 
   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                              SmallVector<MachineOperand,4> Addr,
+                              SmallVectorImpl<MachineOperand> Addr,
                               const TargetRegisterClass *RC,
-                              SmallVector<MachineInstr*,4> &NewMIs) const = 0;
+                              SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
 
   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator MI,
@@ -518,9 +518,9 @@ public:
                                     const TargetRegisterClass *RC) const = 0;
 
   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                               SmallVector<MachineOperand,4> Addr,
+                               SmallVectorImpl<MachineOperand> Addr,
                                const TargetRegisterClass *RC,
-                               SmallVector<MachineInstr*,4> &NewMIs) const = 0;
+                               SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
 
   virtual void copyRegToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
@@ -568,12 +568,12 @@ public:
   /// possible, returns true as well as the new instructions by reference.
   virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
-                                   SmallVector<MachineInstr*, 4> &NewMIs) const{
+                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
     return false;
   }
 
   virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
-                                   SmallVector<SDNode*, 4> &NewNodes) const {
+                                   SmallVectorImpl<SDNode*> &NewNodes) const {
     return false;
   }
 
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 02446e91a9..c448467328 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -183,9 +183,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 }
 
 void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                     SmallVector<MachineOperand,4> Addr,
+                                     SmallVectorImpl<MachineOperand> Addr,
                                      const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == ARM::GPRRegisterClass) {
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
@@ -239,9 +239,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 }
 
 void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                      SmallVector<MachineOperand,4> Addr,
+                                      SmallVectorImpl<MachineOperand> Addr,
                                       const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == ARM::GPRRegisterClass) {
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index cd32eb63db..26602527b2 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -52,9 +52,9 @@ public:
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
@@ -62,9 +62,9 @@ public:
                             const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 7959483cb5..b62f9095c7 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -83,9 +83,9 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 }
 
 void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                       SmallVector<MachineOperand,4> Addr,
+                                       SmallVectorImpl<MachineOperand> Addr,
                                        const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == Alpha::F4RCRegisterClass)
     Opc = Alpha::STS;
@@ -128,9 +128,9 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 }
 
 void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                        SmallVector<MachineOperand,4> Addr,
+                                        SmallVectorImpl<MachineOperand> Addr,
                                         const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == Alpha::F4RCRegisterClass)
     Opc = Alpha::LDS;
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h
index c9bb2dd539..467178de2b 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -34,9 +34,9 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
@@ -44,9 +44,9 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
                             const TargetRegisterClass *RC) const;
   
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   MachineInstr* foldMemoryOperand(MachineInstr *MI, unsigned OpNum, 
                                   int FrameIndex) const;
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 4c944ad69c..c826d4c317 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -61,9 +61,9 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 }
 
 void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                      SmallVector<MachineOperand,4> Addr,
+                                      SmallVectorImpl<MachineOperand> Addr,
                                       const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == IA64::FPRegisterClass) {
     Opc = IA64::STF8;
@@ -113,9 +113,9 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 }
 
 void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                       SmallVector<MachineOperand,4> Addr,
+                                       SmallVectorImpl<MachineOperand> Addr,
                                        const TargetRegisterClass *RC,
-                                       SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == IA64::FPRegisterClass) {
     Opc = IA64::LDF8;
diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h
index c55675250f..3fcd213de1 100644
--- a/lib/Target/IA64/IA64RegisterInfo.h
+++ b/lib/Target/IA64/IA64RegisterInfo.h
@@ -35,9 +35,9 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
@@ -45,9 +45,9 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
                             const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void copyRegToReg(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 2e872932ac..8fd311196f 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -96,9 +96,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 }
 
 void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                      SmallVector<MachineOperand,4> Addr,
+                                      SmallVectorImpl<MachineOperand> Addr,
                                       const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   if (RC != Mips::CPURegsRegisterClass)
     assert(0 && "Can't store this register");
   MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
@@ -128,9 +128,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 }
 
 void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                       SmallVector<MachineOperand,4> Addr,
+                                       SmallVectorImpl<MachineOperand> Addr,
                                        const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   if (RC != Mips::CPURegsRegisterClass)
     assert(0 && "Can't load this register");
   MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h
index 47d1fc2b33..75ae423391 100644
--- a/lib/Target/Mips/MipsRegisterInfo.h
+++ b/lib/Target/Mips/MipsRegisterInfo.h
@@ -38,9 +38,9 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
               MachineBasicBlock::iterator MBBI,
@@ -48,9 +48,9 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
               const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                      unsigned DestReg, const MachineInstr *Orig) const;
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 1e43e79b63..122a8d3d3a 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -106,7 +106,7 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
 static void StoreRegToStackSlot(const TargetInstrInfo &TII,
                                 unsigned SrcReg, int FrameIdx,
                                 const TargetRegisterClass *RC,
-                                SmallVector<MachineInstr*, 4> &NewMIs) {
+                                SmallVectorImpl<MachineInstr*> &NewMIs) {
   if (RC == PPC::GPRCRegisterClass) {
     if (SrcReg != PPC::LR) {
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
@@ -182,9 +182,9 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 }
 
 void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                     SmallVector<MachineOperand,4> Addr,
+                                     SmallVectorImpl<MachineOperand> Addr,
                                      const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   if (Addr[0].isFrameIndex()) {
     StoreRegToStackSlot(TII, SrcReg, Addr[0].getFrameIndex(), RC, NewMIs);
     return;
@@ -223,7 +223,7 @@ void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
 static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
                                  unsigned DestReg, int FrameIdx,
                                  const TargetRegisterClass *RC,
-                                 SmallVector<MachineInstr*, 4> &NewMIs) {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) {
   if (RC == PPC::GPRCRegisterClass) {
     if (DestReg != PPC::LR) {
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
@@ -291,9 +291,9 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 }
 
 void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                      SmallVector<MachineOperand,4> Addr,
+                                      SmallVectorImpl<MachineOperand> Addr,
                                       const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
   if (Addr[0].isFrameIndex()) {
     LoadRegFromStackSlot(TII, DestReg, Addr[0].getFrameIndex(), RC, NewMIs);
     return;
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index e986c1b8d5..b3f49d116a 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -41,9 +41,9 @@ public:
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
@@ -51,9 +51,9 @@ public:
                             const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 7129f43712..3055bf9dfe 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -49,9 +49,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 }
 
 void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                       SmallVector<MachineOperand,4> Addr,
+                                       SmallVectorImpl<MachineOperand> Addr,
                                        const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == SP::IntRegsRegisterClass)
     Opc = SP::STri;
@@ -91,9 +91,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 }
 
 void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                        SmallVector<MachineOperand,4> Addr,
+                                        SmallVectorImpl<MachineOperand> Addr,
                                         const TargetRegisterClass *RC,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = 0;
   if (RC == SP::IntRegsRegisterClass)
     Opc = SP::LDri;
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 39cf6160d6..15a624f263 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -36,9 +36,9 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
@@ -46,9 +46,9 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
                             const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 6e8a543291..7788088685 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -806,9 +806,9 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 }
 
 void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                     SmallVector<MachineOperand,4> Addr,
+                                     SmallVectorImpl<MachineOperand> Addr,
                                      const TargetRegisterClass *RC,
-                                   SmallVector<MachineInstr*,4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = getStoreRegOpcode(RC);
   MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -862,9 +862,9 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 }
 
 void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                      SmallVector<MachineOperand,4> Addr,
+                                      SmallVectorImpl<MachineOperand> Addr,
                                       const TargetRegisterClass *RC,
-                                      SmallVector<MachineInstr*,4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   unsigned Opc = getLoadRegOpcode(RC);
   MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -1119,7 +1119,7 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNu
 
 bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
-                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
     MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
   if (I == MemOp2RegOpTable.end())
@@ -1199,7 +1199,7 @@ bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
 
 bool
 X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
-                                     SmallVector<SDNode*, 4> &NewNodes) const {
+                                     SmallVectorImpl<SDNode*> &NewNodes) const {
   if (!N->isTargetOpcode())
     return false;
 
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 26b52f4530..76045476c2 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -89,9 +89,9 @@ public:
                            const TargetRegisterClass *RC) const;
 
   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                      SmallVector<MachineOperand,4> Addr,
+                      SmallVectorImpl<MachineOperand> Addr,
                       const TargetRegisterClass *RC,
-                      SmallVector<MachineInstr*,4> &NewMIs) const;
+                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
@@ -99,9 +99,9 @@ public:
                             const TargetRegisterClass *RC) const;
 
   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                       SmallVector<MachineOperand,4> Addr,
+                       SmallVectorImpl<MachineOperand> Addr,
                        const TargetRegisterClass *RC,
-                       SmallVector<MachineInstr*,4> &NewMIs) const;
+                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   void copyRegToReg(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,
@@ -137,10 +137,10 @@ public:
   /// possible, returns true as well as the new instructions by reference.
   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
-                           SmallVector<MachineInstr*, 4> &NewMIs) const;
+                           SmallVectorImpl<MachineInstr*> &NewMIs) const;
 
   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
-                           SmallVector<SDNode*, 4> &NewNodes) const;
+                           SmallVectorImpl<SDNode*> &NewNodes) const;
 
   /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.