Make the Node member of SUnit private, and add accessors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59264 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 55 insertions, 47 deletions

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 4facfdab8d..890dc0f149 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -92,7 +92,9 @@ namespace llvm {
   /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
   /// a group of nodes flagged together.
   struct SUnit {
+  private:
     SDNode *Node;                       // Representative node.
+  public:
     SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
     SUnit *OrigNode;                    // If not this, the node from which
                                         // this node was cloned.
@@ -135,6 +137,12 @@ namespace llvm {
         CycleBound(0), Cycle(0), Depth(0), Height(0),
         CopyDstRC(NULL), CopySrcRC(NULL) {}
 
+    /// setNode - Assign the representative SDNode for this SUnit.
+    void setNode(SDNode *N) { Node = N; }
+
+    /// getNode - Return the representative SDNode for this SUnit.
+    SDNode *getNode() const { return Node; }
+
     /// addPred - This adds the specified node as a pred of the current node if
     /// not already.  This returns true if this is a new pred.
     bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 8ef493b06e..7dd8f501aa 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -58,7 +58,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
 }
 
 SUnit *ScheduleDAG::Clone(SUnit *Old) {
-  SUnit *SU = NewSUnit(Old->Node);
+  SUnit *SU = NewSUnit(Old->getNode());
   SU->OrigNode = Old->OrigNode;
   SU->FlaggedNodes = Old->FlaggedNodes;
   SU->Latency = Old->Latency;
@@ -137,7 +137,7 @@ void ScheduleDAG::BuildSchedUnits() {
     
     // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
     // Update the SUnit
-    NodeSUnit->Node = N;
+    NodeSUnit->setNode(N);
     assert(N->getNodeId() == -1 && "Node already inserted!");
     N->setNodeId(NodeSUnit->NodeNum);
 
@@ -147,7 +147,7 @@ void ScheduleDAG::BuildSchedUnits() {
   // Pass 2: add the preds, succs, etc.
   for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
     SUnit *SU = &SUnits[su];
-    SDNode *MainNode = SU->Node;
+    SDNode *MainNode = SU->getNode();
     
     if (MainNode->isMachineOpcode()) {
       unsigned Opc = MainNode->getMachineOpcode();
@@ -209,8 +209,8 @@ void ScheduleDAG::ComputeLatency(SUnit *SU) {
   }
 
   SU->Latency = 0;
-  if (SU->Node->isMachineOpcode()) {
-    unsigned SchedClass = TII->get(SU->Node->getMachineOpcode()).getSchedClass();
+  if (SU->getNode()->isMachineOpcode()) {
+    unsigned SchedClass = TII->get(SU->getNode()->getMachineOpcode()).getSchedClass();
     const InstrStage *S = InstrItins.begin(SchedClass);
     const InstrStage *E = InstrItins.end(SchedClass);
     for (; S != E; ++S)
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index fd09b5c77c..7d5822faae 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -643,7 +643,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain preds
-    if (!I->Dep->Node) {
+    if (!I->Dep->getNode()) {
       // Copy to physical register.
       DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
       assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
@@ -686,10 +686,10 @@ MachineBasicBlock *ScheduleDAG::EmitSchedule() {
     }
     for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
       EmitNode(SU->FlaggedNodes[j], SU->OrigNode != SU, VRBaseMap);
-    if (!SU->Node)
+    if (!SU->getNode())
       EmitCrossRCCopy(SU, CopyVRBaseMap);
     else
-      EmitNode(SU->Node, SU->OrigNode != SU, VRBaseMap);
+      EmitNode(SU->getNode(), SU->OrigNode != SU, VRBaseMap);
   }
 
   return BB;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index c146e15840..51a784e643 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -224,7 +224,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
   if (SU->FlaggedNodes.size())
     return NULL;
 
-  SDNode *N = SU->Node;
+  SDNode *N = SU->getNode();
   if (!N)
     return NULL;
 
@@ -255,10 +255,10 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
     N = NewNodes[1];
     SDNode *LoadNode = NewNodes[0];
     unsigned NumVals = N->getNumValues();
-    unsigned OldNumVals = SU->Node->getNumValues();
+    unsigned OldNumVals = SU->getNode()->getNumValues();
     for (unsigned i = 0; i != NumVals; ++i)
-      DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
-    DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
+      DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
+    DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
                                    SDValue(LoadNode, 1));
 
     SUnit *NewSU = CreateNewSUnit(N);
@@ -305,7 +305,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
          I != E; ++I) {
       if (I->isCtrl)
         ChainPred = I->Dep;
-      else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode))
+      else if (I->Dep->getNode() && I->Dep->getNode()->isOperandOf(LoadNode))
         LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
       else
         NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
@@ -486,7 +486,7 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
   }
 
   for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
-    SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
+    SDNode *Node = (i == 0) ? SU->getNode() : SU->FlaggedNodes[i-1];
     if (!Node || !Node->isMachineOpcode())
       continue;
     const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
@@ -560,7 +560,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
         SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
         if (!NewDef) {
           // Issue expensive cross register class copies.
-          MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
+          MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
           const TargetRegisterClass *RC =
             TRI->getPhysicalRegisterRegClass(Reg, VT);
           const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index de9ae72ff3..8921545e1a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -201,7 +201,7 @@ void ScheduleDAGList::ListScheduleTopDown() {
       SUnit *CurSUnit = AvailableQueue->pop();
       
       // Get the node represented by this SUnit.
-      FoundNode = CurSUnit->Node;
+      FoundNode = CurSUnit->getNode();
       
       // If this is a pseudo op, like copyfromreg, look to see if there is a
       // real target node flagged to it.  If so, use the target node.
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 99c9a22a9e..15fffdfeea 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -215,9 +215,9 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
   for (unsigned i = Sequence.size(); i != 0; ) {
     --i;
     SUnit *SU = Sequence[i];
-    if (!SU || !SU->Node) continue;
+    if (!SU || !SU->getNode()) continue;
     if (SU->isCommutable) {
-      unsigned Opc = SU->Node->getMachineOpcode();
+      unsigned Opc = SU->getNode()->getMachineOpcode();
       const TargetInstrDesc &TID = TII->get(Opc);
       unsigned NumRes = TID.getNumDefs();
       unsigned NumOps = TID.getNumOperands() - NumRes;
@@ -225,7 +225,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
         if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
           continue;
 
-        SDNode *OpN = SU->Node->getOperand(j).getNode();
+        SDNode *OpN = SU->getNode()->getOperand(j).getNode();
         SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
         if (OpSU && OperandSeen.count(OpSU) == 1) {
           // Ok, so SU is not the last use of OpSU, but SU is two-address so
@@ -234,7 +234,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
           bool DoCommute = true;
           for (unsigned k = 0; k < NumOps; ++k) {
             if (k != j) {
-              OpN = SU->Node->getOperand(k).getNode();
+              OpN = SU->getNode()->getOperand(k).getNode();
               OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
               if (OpSU && OperandSeen.count(OpSU) == 1) {
                 DoCommute = false;
@@ -243,7 +243,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
             }
           }
           if (DoCommute)
-            CommuteSet.insert(SU->Node);
+            CommuteSet.insert(SU->getNode());
         }
 
         // Only look at the first use&def node for now.
@@ -629,7 +629,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
   if (SU->FlaggedNodes.size())
     return NULL;
 
-  SDNode *N = SU->Node;
+  SDNode *N = SU->getNode();
   if (!N)
     return NULL;
 
@@ -660,10 +660,10 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
     N = NewNodes[1];
     SDNode *LoadNode = NewNodes[0];
     unsigned NumVals = N->getNumValues();
-    unsigned OldNumVals = SU->Node->getNumValues();
+    unsigned OldNumVals = SU->getNode()->getNumValues();
     for (unsigned i = 0; i != NumVals; ++i)
-      DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
-    DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
+      DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
+    DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
                                    SDValue(LoadNode, 1));
 
     // LoadNode may already exist. This can happen when there is another
@@ -710,7 +710,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
          I != E; ++I) {
       if (I->isCtrl)
         ChainPred = I->Dep;
-      else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode))
+      else if (I->Dep->getNode() && I->Dep->getNode()->isOperandOf(LoadNode))
         LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
       else
         NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
@@ -904,7 +904,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
   }
 
   for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
-    SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
+    SDNode *Node = (i == 0) ? SU->getNode() : SU->FlaggedNodes[i-1];
     if (!Node || !Node->isMachineOpcode())
       continue;
     const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
@@ -1014,7 +1014,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
         SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
         if (!NewDef) {
           // Issue expensive cross register class copies.
-          MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
+          MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
           const TargetRegisterClass *RC =
             TRI->getPhysicalRegisterRegClass(Reg, VT);
           const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
@@ -1263,7 +1263,7 @@ namespace {
 }  // end anonymous namespace
 
 static inline bool isCopyFromLiveIn(const SUnit *SU) {
-  SDNode *N = SU->Node;
+  SDNode *N = SU->getNode();
   return N && N->getOpcode() == ISD::CopyFromReg &&
     N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
 }
@@ -1305,7 +1305,7 @@ CalcNodeTDSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
   if (SethiUllmanNumber != 0)
     return SethiUllmanNumber;
 
-  unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
+  unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
   if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
     SethiUllmanNumber = 0xffff;
   else if (SU->NumSuccsLeft == 0)
@@ -1434,7 +1434,7 @@ namespace {
 
     unsigned getNodePriority(const SUnit *SU) const {
       assert(SU->NodeNum < SethiUllmanNumbers.size());
-      unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
+      unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
       if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
         // CopyFromReg should be close to its def because it restricts
         // allocation choices. But if it is a livein then perhaps we want it
@@ -1569,7 +1569,7 @@ static unsigned closestSucc(const SUnit *SU) {
     unsigned Cycle = I->Dep->Cycle;
     // If there are bunch of CopyToRegs stacked up, they should be considered
     // to be at the same position.
-    if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg)
+    if (I->Dep->getNode() && I->Dep->getNode()->getOpcode() == ISD::CopyToReg)
       Cycle = closestSucc(I->Dep)+1;
     if (Cycle > MaxCycle)
       MaxCycle = Cycle;
@@ -1585,13 +1585,13 @@ static unsigned calcMaxScratches(const SUnit *SU) {
   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain preds
-    if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
+    if (!I->Dep->getNode() || I->Dep->getNode()->getOpcode() != ISD::CopyFromReg)
       Scratches++;
   }
   for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain succs
-    if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
+    if (!I->Dep->getNode() || I->Dep->getNode()->getOpcode() != ISD::CopyToReg)
       Scratches += 10;
   }
   return Scratches;
@@ -1663,13 +1663,13 @@ bu_ls_rr_fast_sort::operator()(const SUnit *left, const SUnit *right) const {
 bool
 BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) {
   if (SU->isTwoAddress) {
-    unsigned Opc = SU->Node->getMachineOpcode();
+    unsigned Opc = SU->getNode()->getMachineOpcode();
     const TargetInstrDesc &TID = TII->get(Opc);
     unsigned NumRes = TID.getNumDefs();
     unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned i = 0; i != NumOps; ++i) {
       if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
-        SDNode *DU = SU->Node->getOperand(i).getNode();
+        SDNode *DU = SU->getNode()->getOperand(i).getNode();
         if (DU->getNodeId() != -1 &&
             Op->OrigNode == &(*SUnits)[DU->getNodeId()])
           return true;
@@ -1687,7 +1687,7 @@ static bool hasCopyToRegUse(const SUnit *SU) {
        I != E; ++I) {
     if (I->isCtrl) continue;
     const SUnit *SuccSU = I->Dep;
-    if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
+    if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg)
       return true;
   }
   return false;
@@ -1698,12 +1698,12 @@ static bool hasCopyToRegUse(const SUnit *SU) {
 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
                                   const TargetInstrInfo *TII,
                                   const TargetRegisterInfo *TRI) {
-  SDNode *N = SuccSU->Node;
+  SDNode *N = SuccSU->getNode();
   unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
   const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
   assert(ImpDefs && "Caller should check hasPhysRegDefs");
   const unsigned *SUImpDefs =
-    TII->get(SU->Node->getMachineOpcode()).getImplicitDefs();
+    TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
   if (!SUImpDefs)
     return false;
   for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
@@ -1735,7 +1735,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
     if (!SU->isTwoAddress)
       continue;
 
-    SDNode *Node = SU->Node;
+    SDNode *Node = SU->getNode();
     if (!Node || !Node->isMachineOpcode() || SU->FlaggedNodes.size() > 0)
       continue;
 
@@ -1745,7 +1745,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
     unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned j = 0; j != NumOps; ++j) {
       if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
-        SDNode *DU = SU->Node->getOperand(j).getNode();
+        SDNode *DU = SU->getNode()->getOperand(j).getNode();
         if (DU->getNodeId() == -1)
           continue;
         const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
@@ -1760,7 +1760,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
           // depth and height.
           if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1)
             continue;
-          if (!SuccSU->Node || !SuccSU->Node->isMachineOpcode())
+          if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
             continue;
           // Don't constrain nodes with physical register defs if the
           // predecessor can clobber them.
@@ -1770,7 +1770,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
           }
           // Don't constraint extract_subreg / insert_subreg these may be
           // coalesced away. We don't them close to their uses.
-          unsigned SuccOpc = SuccSU->Node->getMachineOpcode();
+          unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
           if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
               SuccOpc == TargetInstrInfo::INSERT_SUBREG)
             continue;
@@ -1828,8 +1828,8 @@ static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
   unsigned LPriority = SPQ->getNodePriority(left);
   unsigned RPriority = SPQ->getNodePriority(right);
-  bool LIsTarget = left->Node && left->Node->isMachineOpcode();
-  bool RIsTarget = right->Node && right->Node->isMachineOpcode();
+  bool LIsTarget = left->getNode() && left->getNode()->isMachineOpcode();
+  bool RIsTarget = right->getNode() && right->getNode()->isMachineOpcode();
   bool LIsFloater = LIsTarget && left->NumPreds == 0;
   bool RIsFloater = RIsTarget && right->NumPreds == 0;
   unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 22791d3dc7..1f45729462 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -438,8 +438,8 @@ std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
                                                       G->DAG) + "\n";
   }
 
-  if (SU->Node)
-    Op += DOTGraphTraits<SelectionDAG*>::getNodeLabel(SU->Node, G->DAG);
+  if (SU->getNode())
+    Op += DOTGraphTraits<SelectionDAG*>::getNodeLabel(SU->getNode(), G->DAG);
   else
     Op += "<CROSS RC COPY>";