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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-18 22:10:11 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-18 22:10:11 +0000 |
| commit | 4b8921d1c7bf17a496933dd1a80077404e14e841 (patch) | |
| tree | 187451be51cd746f27a63631719b2987515688c5 | |
| parent | a845706dc1cebfe75913832e07ef114519a879d6 (diff) | |
Use the new 'defm' class inheritance in SSE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 56 |
1 files changed, 24 insertions, 32 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 8ffb8e8cd3..e5e9d59e34 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -672,29 +672,25 @@ let Constraints = "$src1 = $dst" in { multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in { + let Constraints = "", isAsmParserOnly = 1 in { // Scalar operation, reg+reg. - let Prefix = 12 /* XS */ in - defm V#NAME#SS : sse12_fp_scalar<opc, + defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - OpNode, FR32, f32mem>; + OpNode, FR32, f32mem>, XS, VEX_4V; - let Prefix = 11 /* XD */ in - defm V#NAME#SD : sse12_fp_scalar<opc, + defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - OpNode, FR64, f64mem>; + OpNode, FR64, f64mem>, XD, VEX_4V; } let Constraints = "$src1 = $dst" in { // Scalar operation, reg+reg. - let Prefix = 12 /* XS */ in - defm SS : sse12_fp_scalar<opc, - !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), - OpNode, FR32, f32mem>; - let Prefix = 11 /* XD */ in - defm SD : sse12_fp_scalar<opc, - !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), - OpNode, FR64, f64mem>; + defm SS : sse12_fp_scalar<opc, + !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), + OpNode, FR32, f32mem>, XS; + defm SD : sse12_fp_scalar<opc, + !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), + OpNode, FR64, f64mem>, XD; } // Vector operation, reg+reg. @@ -857,29 +853,25 @@ let Constraints = "$src1 = $dst" in { multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in { + let Constraints = "", isAsmParserOnly = 1 in { // Scalar operation, reg+reg. - let Prefix = 12 /* XS */ in - defm V#NAME#SS : sse12_fp_scalar<opc, - !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - OpNode, FR32, f32mem>; + defm V#NAME#SS : sse12_fp_scalar<opc, + !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + OpNode, FR32, f32mem>, XS, VEX_4V; - let Prefix = 11 /* XD */ in - defm V#NAME#SD : sse12_fp_scalar<opc, - !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - OpNode, FR64, f64mem>; + defm V#NAME#SD : sse12_fp_scalar<opc, + !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + OpNode, FR64, f64mem>, XD, VEX_4V; } let Constraints = "$src1 = $dst" in { // Scalar operation, reg+reg. - let Prefix = 12 /* XS */ in - defm SS : sse12_fp_scalar<opc, - !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), - OpNode, FR32, f32mem>; - let Prefix = 11 /* XD */ in - defm SD : sse12_fp_scalar<opc, - !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), - OpNode, FR64, f64mem>; + defm SS : sse12_fp_scalar<opc, + !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), + OpNode, FR32, f32mem>, XS; + defm SD : sse12_fp_scalar<opc, + !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), + OpNode, FR64, f64mem>, XD; } // Vector operation, reg+reg. |