diff options
| author | Andrew Trick <atrick@apple.com> | 2012-07-28 01:48:15 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-07-28 01:48:15 +0000 |
| commit | 4b72ada1f4c1c90ead331a650956e7b14450080e (patch) | |
| tree | 7e5cd559558cc36b7b10c682e4ac94946e0cd815 | |
| parent | 08f6ef6a7807250d84446661b7a6ec4afa762099 (diff) | |
Reenable a basic SSA DAG builder optimization.
Jakob fixed ProcessImplicifDefs in r159149.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160910 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 110f478f48..5b40cb4a7e 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -411,12 +411,11 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { const MachineInstr *MI = SU->getInstr(); unsigned Reg = MI->getOperand(OperIdx).getReg(); - // SSA defs do not have output/anti dependencies. + // Singly defined vregs do not have output/anti dependencies. // The current operand is a def, so we have at least one. - // - // FIXME: This optimization is disabled pending PR13112. - //if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) - // return; + // Check here if there are any others... + if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) + return; // Add output dependence to the next nearest def of this vreg. // |