diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-04-02 05:03:24 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-02 05:03:24 +0000 |
| commit | 43fdea070cd54094b5c3b69ce5a25c04d93c91af (patch) | |
| tree | 231f7fd2a551ab418a2e458e40626a1d41d12c0a | |
| parent | 2c8086f4b9916b2d02842be5e375276023225fba (diff) | |
This target doesn't support fabs/fneg yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64ISelPattern.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelPattern.cpp | 4 |
4 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index ba5178b621..7242f8f1fd 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -75,6 +75,10 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); + //Doesn't work yet setOperationAction(ISD::SETCC , MVT::f32, Promote); diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 16607cbcc3..bb31fc7f5c 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -80,6 +80,9 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); computeRegisterProperties(); diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index a6ebbadf56..751b553357 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -53,6 +53,10 @@ namespace { // PowerPC has an i16 but no i8 (or i1) SEXTLOAD setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); + + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); addLegalFPImmediate(+0.0); // Necessary for FSEL addLegalFPImmediate(-0.0); // diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index ff23e66c04..c81b7794f7 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -63,6 +63,10 @@ namespace { setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); setOperationAction(ISD::SREM , MVT::f64 , Expand); + + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); // These should be promoted to a larger select which is supported. /**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote); |