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authorJim Grosbach <grosbach@apple.com>2010-12-08 23:12:09 +0000
committerJim Grosbach <grosbach@apple.com>2010-12-08 23:12:09 +0000
commit37474e6d68b42b0d1f4299c8588893bfaa3d0d09 (patch)
tree76df99fbd5bd82e6738c2fad7a057d5f0aa02c18
parent07e9b26371c1045a5b1dde55fcaa8e2753eb0377 (diff)
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121310 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td10
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 6e71dcb669..108a96e4d0 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1195,12 +1195,16 @@ def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
}
def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
+ bits<4> Rd;
+ bits<12> imm;
let Inst{31-27} = 0b11110;
- let Inst{25} = 1;
- let Inst{24-21} = 0b0101;
- let Inst{20} = 0; // The S bit.
+ let Inst{26} = imm{11};
+ let Inst{25-20} = 0b101010;
let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0;
+ let Inst{14-12} = imm{10-8};
+ let Inst{11-8} = Rd;
+ let Inst{7-0} = imm{7-0};
}
// SUB r, sp, so_reg