Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.

(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*.  Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21599 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 144 insertions, 66 deletions

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 39d4ef4ffc..f3d41cea15 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -162,6 +162,8 @@ public:
   SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
                     SDOperand N1, SDOperand N2, SDOperand N3);
   SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
+                    SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
+  SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
                     std::vector<SDOperand> &Children);
 
   // getNode - These versions take an extra value type for extending and
@@ -172,11 +174,16 @@ public:
                     SDOperand N, MVT::ValueType EVT);
   SDOperand getNode(unsigned Opcode, MVT::ValueType VT, SDOperand N1,
                     SDOperand N2, SDOperand N3, MVT::ValueType EVT);
+  SDOperand getNode(unsigned Opcode, MVT::ValueType VT, SDOperand N1,
+                    SDOperand N2, SDOperand N3, SDOperand N4, MVT::ValueType EVT);
 
   /// getLoad - Loads are not normal binary operators: their result type is not
   /// determined by their operands, and they produce a value AND a token chain.
   ///
-  SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr);
+  SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, SDOperand SV);
+
+  // getSrcValue - construct a node to track a Value* through the backend
+  SDOperand getSrcValue(const Value* I);
 
   void replaceAllUsesWith(SDOperand Old, SDOperand New) {
     assert(Old != New && "RAUW self!");
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 35993d986a..1df651381c 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -20,6 +20,7 @@
 #define LLVM_CODEGEN_SELECTIONDAGNODES_H
 
 #include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/Value.h"
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/iterator"
@@ -251,6 +252,11 @@ namespace ISD {
     // PCMARKER - This corresponds to the pcmarker intrinsic.
     PCMARKER,
 
+    // SRCVALUE - This corresponds to a Value*, and is used to carry associate
+    // memory operations with their corrosponding load.  This lets one use the
+    // pointer analysis information in the backend
+    SRCVALUE,
+
     // BUILTIN_OP_END - This must be the last enum value in this list.
     BUILTIN_OP_END,
   };
@@ -529,6 +535,22 @@ protected:
     N1.Val->Uses.push_back(this); N2.Val->Uses.push_back(this);
     N3.Val->Uses.push_back(this);
   }
+  SDNode(unsigned NT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4)
+    : NodeType(NT) {
+    unsigned ND = N1.Val->getNodeDepth();
+    if (ND < N2.Val->getNodeDepth())
+      ND = N2.Val->getNodeDepth();
+    if (ND < N3.Val->getNodeDepth())
+      ND = N3.Val->getNodeDepth();
+    if (ND < N4.Val->getNodeDepth())
+      ND = N4.Val->getNodeDepth();
+    NodeDepth = ND+1;
+
+    Operands.reserve(3); Operands.push_back(N1); Operands.push_back(N2);
+    Operands.push_back(N3); Operands.push_back(N4);
+    N1.Val->Uses.push_back(this); N2.Val->Uses.push_back(this);
+    N3.Val->Uses.push_back(this); N4.Val->Uses.push_back(this);
+  }
   SDNode(unsigned NT, std::vector<SDOperand> &Nodes) : NodeType(NT) {
     Operands.swap(Nodes);
     unsigned ND = 0;
@@ -724,6 +746,22 @@ public:
   }
 };
 
+class SrcValueSDNode : public SDNode {
+  const Value *V;
+protected:
+  friend class SelectionDAG;
+  SrcValueSDNode(const Value* v)
+    : SDNode(ISD::SRCVALUE, MVT::Other), V(v) {}
+
+public:
+  const Value *getValue() const { return V; }
+
+  static bool classof(const SrcValueSDNode *) { return true; }
+  static bool classof(const SDNode *N) {
+    return N->getOpcode() == ISD::SRCVALUE;
+  }
+};
+
 
 class RegSDNode : public SDNode {
   unsigned Reg;
@@ -791,13 +829,14 @@ protected:
     setValueTypes(VT1);
   }
   MVTSDNode(unsigned Opc, MVT::ValueType VT1, MVT::ValueType VT2,
-            SDOperand Op0, SDOperand Op1, MVT::ValueType EVT)
-    : SDNode(Opc, Op0, Op1), ExtraValueType(EVT) {
+            SDOperand Op0, SDOperand Op1, SDOperand Op2, MVT::ValueType EVT)
+    : SDNode(Opc, Op0, Op1, Op2), ExtraValueType(EVT) {
     setValueTypes(VT1, VT2);
   }
+
   MVTSDNode(unsigned Opc, MVT::ValueType VT,
-            SDOperand Op0, SDOperand Op1, SDOperand Op2, MVT::ValueType EVT)
-    : SDNode(Opc, Op0, Op1, Op2), ExtraValueType(EVT) {
+            SDOperand Op0, SDOperand Op1, SDOperand Op2, SDOperand Op3, MVT::ValueType EVT)
+    : SDNode(Opc, Op0, Op1, Op2, Op3), ExtraValueType(EVT) {
     setValueTypes(VT);
   }
 public:
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 12938e6e57..20912583d7 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -290,9 +290,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
                                             TLI.getPointerTy());
       if (Extend) {
         Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx,
-                             MVT::f32);
+                             DAG.getSrcValue(NULL), MVT::f32);
       } else {
-        Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx);
+        Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
       }
     }
     break;
@@ -428,9 +428,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
   case ISD::LOAD:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
+
     if (Tmp1 != Node->getOperand(0) ||
         Tmp2 != Node->getOperand(1))
-      Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2);
+      Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, Node->getOperand(2));
     else
       Result = SDOperand(Node, 0);
 
@@ -452,7 +453,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case TargetLowering::Promote:
       assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
       Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
-                           Tmp1, Tmp2, MVT::i8);
+                           Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
       // Since loads produce two values, make sure to remember that we legalized
       // both of them.
       AddLegalizedOperand(SDOperand(Node, 0), Result);
@@ -463,7 +464,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       if (Tmp1 != Node->getOperand(0) ||
           Tmp2 != Node->getOperand(1))
         Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
-                             Tmp1, Tmp2, SrcVT);
+                             Tmp1, Tmp2, Node->getOperand(2), SrcVT);
       else
         Result = SDOperand(Node, 0);
 
@@ -478,7 +479,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // Turn the unsupported load into an EXTLOAD followed by an explicit
       // zero/sign extend inreg.
       Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
-                           Tmp1, Tmp2, SrcVT);
+                           Tmp1, Tmp2, Node->getOperand(2), SrcVT);
       SDOperand ValRes;
       if (Node->getOpcode() == ISD::SEXTLOAD)
         ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
@@ -591,8 +592,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           float    F;
         } V;
         V.F = CFP->getValue();
-        Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
-                             DAG.getConstant(V.I, MVT::i32), Tmp2);
+        Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 
+                              DAG.getConstant(V.I, MVT::i32), Tmp2, Node->getOperand(3));
       } else {
         assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
         union {
@@ -600,8 +601,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           double   F;
         } V;
         V.F = CFP->getValue();
-        Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
-                             DAG.getConstant(V.I, MVT::i64), Tmp2);
+        Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 
+                             DAG.getConstant(V.I, MVT::i64), Tmp2, Node->getOperand(3));
       }
       Node = Result.Val;
     }
@@ -611,14 +612,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       SDOperand Val = LegalizeOp(Node->getOperand(1));
       if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
           Tmp2 != Node->getOperand(2))
-        Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2);
+        Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, Node->getOperand(3));
       break;
     }
     case Promote:
       // Truncate the value and store the result.
       Tmp3 = PromoteOp(Node->getOperand(1));
       Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
-                           Node->getOperand(1).getValueType());
+                           Node->getOperand(3),
+                           Node->getOperand(1).getValueType()); 
       break;
 
     case Expand:
@@ -628,14 +630,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       if (!TLI.isLittleEndian())
         std::swap(Lo, Hi);
 
-      Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2);
+      Lo = DAG.getNode(ISD::STORE, MVT::Other,Tmp1, Lo, Tmp2,Node->getOperand(3));
 
       unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
       Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
                          getIntPtrConstant(IncrementSize));
       assert(isTypeLegal(Tmp2.getValueType()) &&
              "Pointers must be legal!");
-      Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2);
+      //Again, claiming both parts of the store came form the same Instr
+      Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, Node->getOperand(3));
+                              
       Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
       break;
     }
@@ -655,6 +659,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
           Tmp3 != Node->getOperand(2))
         Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
+                             Node->getOperand(3),
                              cast<MVTSDNode>(Node)->getExtraValueType());
       break;
     case Promote:
@@ -1138,9 +1143,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
         SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
         Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
-                             Node->getOperand(0), StackSlot, ExtraVT);
+                             Node->getOperand(0), StackSlot, DAG.getSrcValue(NULL), ExtraVT);
         Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
-                             Result, StackSlot, ExtraVT);
+                             Result, StackSlot, DAG.getSrcValue(NULL), ExtraVT);
       } else {
         assert(0 && "Unknown op");
       }
@@ -1404,9 +1409,9 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Tmp2 = LegalizeOp(Node->getOperand(1));   // Legalize the pointer.
     // FIXME: When the DAG combiner exists, change this to use EXTLOAD!
     if (MVT::isInteger(NVT))
-      Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, VT);
+      Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2), VT);
     else
-      Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, VT);
+      Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2), VT);
 
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
@@ -1846,11 +1851,11 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
     CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
     SDOperand FudgeInReg;
     if (DestTy == MVT::f32)
-      FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx);
+      FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
     else {
       assert(DestTy == MVT::f64 && "Unexpected conversion");
       FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
-                               CPIdx, MVT::f32);
+                               CPIdx, DAG.getSrcValue(NULL), MVT::f32);
     }
     return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg);
   }
@@ -1941,13 +1946,15 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
   case ISD::LOAD: {
     SDOperand Ch = LegalizeOp(Node->getOperand(0));   // Legalize the chain.
     SDOperand Ptr = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
-    Lo = DAG.getLoad(NVT, Ch, Ptr);
+    Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
 
     // Increment the pointer to the other half.
     unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
                       getIntPtrConstant(IncrementSize));
-    Hi = DAG.getLoad(NVT, Ch, Ptr);
+    //Is this safe?  declaring that the two parts of the split load  
+    //are from the same instruction?
+    Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
 
     // Build a factor node to remember that this load is independent of the
     // other one.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e56ffec44f..2a88270965 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1174,10 +1174,11 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
 }
 
 SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
-                                SDOperand Chain, SDOperand Ptr) {
+                                SDOperand Chain, SDOperand Ptr, 
+                                SDOperand SV) {
   SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))];
   if (N) return SDOperand(N, 0);
-  N = new SDNode(ISD::LOAD, Chain, Ptr);
+  N = new SDNode(ISD::LOAD, Chain, Ptr, SV);
 
   // Loads have a token chain.
   N->setValueTypes(VT, MVT::Other);
@@ -1185,9 +1186,9 @@ SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
   return SDOperand(N, 0);
 }
 
-
 SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
                                 SDOperand N1, SDOperand N2, SDOperand N3) {
+  assert(Opcode != ISD::STORE && "Store shouldn't use this anymore");
   // Perform various simplifications.
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
   ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
@@ -1315,6 +1316,27 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
 }
 
 SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
+                                SDOperand N1, SDOperand N2, SDOperand N3, 
+                                SDOperand N4) {
+  assert(Opcode == ISD::STORE && "Only stores should use this");
+
+  SDNode *N = new SDNode(Opcode, N1, N2, N3, N4);
+  N->setValueTypes(VT);
+
+  // FIXME: memoize NODES
+  AllNodes.push_back(N);
+  return SDOperand(N, 0);
+}
+
+SDOperand SelectionDAG::getSrcValue(const Value* v) {
+  SDNode *N = new SrcValueSDNode(v);
+  N->setValueTypes(MVT::Other);
+  // FIXME: memoize NODES
+  AllNodes.push_back(N);
+  return SDOperand(N, 0);
+}
+
+SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
                                 std::vector<SDOperand> &Children) {
   switch (Children.size()) {
   case 0: return getNode(Opcode, VT);
@@ -1419,7 +1441,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
 }
 
 SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
-                                SDOperand N2, MVT::ValueType EVT) {
+                                SDOperand N2, SDOperand N3, MVT::ValueType EVT) {
   switch (Opcode) {
   default:  assert(0 && "Bad opcode for this accessor!");
   case ISD::EXTLOAD:
@@ -1428,7 +1450,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
     // If they are asking for an extending load from/to the same thing, return a
     // normal load.
     if (VT == EVT)
-      return getNode(ISD::LOAD, VT, N1, N2);
+      return getLoad(VT, N1, N2, N3);
     assert(EVT < VT && "Should only be an extending load, not truncating!");
     assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) &&
            "Cannot sign/zero extend a FP load!");
@@ -1443,16 +1465,17 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
   NN.EVT = EVT;
   NN.Ops.push_back(N1);
   NN.Ops.push_back(N2);
+  NN.Ops.push_back(N3);
 
   SDNode *&N = MVTSDNodes[NN];
   if (N) return SDOperand(N, 0);
-  N = new MVTSDNode(Opcode, VT, MVT::Other, N1, N2, EVT);
+  N = new MVTSDNode(Opcode, VT, MVT::Other, N1, N2, N3, EVT);
   AllNodes.push_back(N);
   return SDOperand(N, 0);
 }
 
 SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
-                                SDOperand N2, SDOperand N3, MVT::ValueType EVT) {
+                                SDOperand N2, SDOperand N3, SDOperand N4, MVT::ValueType EVT) {
   switch (Opcode) {
   default:  assert(0 && "Bad opcode for this accessor!");
   case ISD::TRUNCSTORE:
@@ -1467,7 +1490,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
     // Also for ConstantFP?
 #endif
     if (N1.getValueType() == EVT)       // Normal store?
-      return getNode(ISD::STORE, VT, N1, N2, N3);
+      return getNode(ISD::STORE, VT, N1, N2, N3, N4);
     assert(N2.getValueType() > EVT && "Not a truncation?");
     assert(MVT::isInteger(N2.getValueType()) == MVT::isInteger(EVT) &&
            "Can't do FP-INT conversion!");
@@ -1481,10 +1504,11 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
   NN.Ops.push_back(N1);
   NN.Ops.push_back(N2);
   NN.Ops.push_back(N3);
+  NN.Ops.push_back(N4);
 
   SDNode *&N = MVTSDNodes[NN];
   if (N) return SDOperand(N, 0);
-  N = new MVTSDNode(Opcode, VT, N1, N2, N3, EVT);
+  N = new MVTSDNode(Opcode, VT, N1, N2, N3, N4, EVT);
   AllNodes.push_back(N);
   return SDOperand(N, 0);
 }
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 1697ad39ff..295dd35c57 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -623,7 +623,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
     Root = DAG.getRoot();
   }
 
-  SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr);
+  SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr, DAG.getSrcValue(&I));
   setValue(&I, L);
 
   if (I.isVolatile())
@@ -637,7 +637,8 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
   Value *SrcV = I.getOperand(0);
   SDOperand Src = getValue(SrcV);
   SDOperand Ptr = getValue(I.getOperand(1));
-  DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr));
+  //  DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr));
+  DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr, DAG.getSrcValue(&I)));
 }
 
 void SelectionDAGLowering::visitCall(CallInst &I) {
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 450de9f491..e2e863deac 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -229,7 +229,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       //from this parameter
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
       argt = newroot = DAG.getLoad(getValueType(I->getType()),
-                                   DAG.getEntryNode(), FIN);
+                                   DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     }
     ++count;
     LS.push_back(newroot.getValue(1));
@@ -245,14 +245,14 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       SDOperand argt = DAG.getCopyFromReg(Vreg, MVT::i64, Chain);
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
       SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI));
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL)));
 
       Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
       BuildMI(&BB, Alpha::CPYS, 2, Vreg).addReg(args_float[i]).addReg(args_float[i]);
       argt = DAG.getCopyFromReg(Vreg, MVT::f64, Chain);
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI));
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL)));
     }
 
   // If the function takes variable number of arguments, make a frame index for
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 8580febe9b..c3675a0da0 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -223,7 +223,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         //from this parameter
         SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
         argt = newroot = DAG.getLoad(getValueType(I->getType()),
-            DAG.getEntryNode(), FIN);
+                                     DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
       }
       ++count;
       DAG.setRoot(newroot.getValue(1));
@@ -378,7 +378,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     unsigned Amt;
     if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index e5c2f40e3c..1e72bf0ba6 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -176,7 +176,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
       FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
                         DAG.getConstant(SubregOffset, MVT::i64));
-      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     }
 
     // Every 4 bytes of argument space consumes one of the GPRs available for
@@ -204,7 +204,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot());
       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
-                                    Val, FIN);
+                                    Val, FIN, DAG.getSrcValue(NULL));
       MemOps.push_back(Store);
       // Increment the address by eight for the next argument to store
       SDOperand PtrOff = DAG.getConstant(8, getPointerTy());
@@ -285,7 +285,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
           --GPR_remaining;
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 8;
         break;
@@ -296,11 +296,11 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
           --FPR_remaining;
           if (isVarArg) {
             SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff);
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL));
             MemOps.push_back(Store);
             // Float varargs are always shadowed in available integer registers
             if (GPR_remaining > 0) {
-              SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff, DAG.getSrcValue(NULL));
               MemOps.push_back(Load);
               args_to_use.push_back(Load);
               --GPR_remaining;
@@ -315,7 +315,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
           }
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 8;
         break;
@@ -351,7 +351,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
                          DAG.getConstant(8, VAList.getValueType()));
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index a516a8b3c8..40a2610f2c 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -164,7 +164,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         } else {
           int FI = MFI->CreateFixedObject(4, ArgOffset+4);
           SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
-          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN);
+          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
         }
         // Build the outgoing arg thingy
         argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
@@ -199,7 +199,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
                         DAG.getConstant(SubregOffset, MVT::i32));
-      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     }
 
     // Every 4 bytes of argument space consumes one of the GPRs available for
@@ -229,7 +229,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       MF.addLiveIn(GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
-                                    Val, FIN);
+                                    Val, FIN, DAG.getSrcValue(NULL));
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
       SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
@@ -343,7 +343,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
           --GPR_remaining;
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                       Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 4;
         break;
@@ -365,11 +365,11 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
             SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
             PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
             MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                            Lo, PtrOff));
+                                         Lo, PtrOff, DAG.getSrcValue(NULL)));
           }
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                       Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 8;
         break;
@@ -380,11 +380,11 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
           --FPR_remaining;
           if (isVarArg) {
             SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff);
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL));
             MemOps.push_back(Store);
             // Float varargs are always shadowed in available integer registers
             if (GPR_remaining > 0) {
-              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL));
               MemOps.push_back(Load);
               args_to_use.push_back(Load);
               --GPR_remaining;
@@ -392,7 +392,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
             if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
               SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
               PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
-              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL));
               MemOps.push_back(Load);
               args_to_use.push_back(Load);
               --GPR_remaining;
@@ -412,7 +412,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
           }
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                       Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
         break;
@@ -448,7 +448,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     unsigned Amt;
     if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index e92ef0ab35..bb9e901e1e 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -141,7 +141,7 @@ X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     // dead loads.
     SDOperand ArgValue;
     if (!I->use_empty())
-      ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+      ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     else {
       if (MVT::isInteger(ObjectVT))
         ArgValue = DAG.getConstant(0, ObjectVT);
@@ -239,13 +239,13 @@ X86TargetLowering::LowerCallTo(SDOperand Chain,
       case MVT::i32:
       case MVT::f32:
         Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                     Args[i].first, PtrOff));
+                                     Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         ArgOffset += 4;
         break;
       case MVT::i64:
       case MVT::f64:
         Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                     Args[i].first, PtrOff));
+                                     Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         ArgOffset += 8;
         break;
       }
@@ -278,7 +278,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     unsigned Amt;
     if (ArgVT == MVT::i32)
@@ -312,7 +312,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
 
     if (!isFrameAddress)
       // Just load the return address
-      Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI);
+      Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, DAG.getSrcValue(NULL));
     else
       Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
                            DAG.getConstant(4, MVT::i32));