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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-01-03 22:34:31 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-01-03 22:34:31 +0000 |
| commit | 2d44e02533cdc2ae011121ef651dda93769ced2b (patch) | |
| tree | 2891d1ff4346c4652bfef4117a68445809531d27 | |
| parent | c2d064f0283504d7fe91369021bfd44ce5c8eb2a (diff) | |
Assert when reserved registers have been assigned.
This can only happen if the set of reserved registers changes during
register allocation.
<rdar://problem/10625436>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147486 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/VirtRegMap.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 1a78db7107..35834aa205 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -112,6 +112,9 @@ void VirtRegMap::rewrite(SlotIndexes *Indexes) { SmallVector<unsigned, 8> SuperDeads; SmallVector<unsigned, 8> SuperDefs; SmallVector<unsigned, 8> SuperKills; +#ifndef NDEBUG + BitVector Reserved = TRI->getReservedRegs(*MF); +#endif for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end(); MBBI != MBBE; ++MBBI) { @@ -129,6 +132,7 @@ void VirtRegMap::rewrite(SlotIndexes *Indexes) { unsigned VirtReg = MO.getReg(); unsigned PhysReg = getPhys(VirtReg); assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg"); + assert(!Reserved.test(PhysReg) && "Reserved register assignment"); // Preserve semantics of sub-register operands. if (MO.getSubReg()) { |