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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-02-19 15:22:45 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-19 15:22:45 +0000 |
| commit | 2b4b68d9365e7003fb7404aca2540b5372d7791b (patch) | |
| tree | ba4ebb35889ce1e799912189ee4a32ece6ae294f | |
| parent | 23339b68e224cedac1e7025ba8bca3e3eb127fab (diff) | |
R600: Mark all members of the TRegMem register class as reserved
This stops the Machine Verifier from complaining about uses of undefined
physical registers.
NOTE: This is a candidate for the Mesa stable branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175518 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.cpp b/lib/Target/R600/R600RegisterInfo.cpp index 33e858dc04..bbd7995d7d 100644 --- a/lib/Target/R600/R600RegisterInfo.cpp +++ b/lib/Target/R600/R600RegisterInfo.cpp @@ -49,6 +49,12 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(*I); } + for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(), + E = AMDGPU::TRegMemRegClass.end(); + I != E; ++I) { + Reserved.set(*I); + } + const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII); std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF); for (std::vector<unsigned>::iterator I = IndirectRegs.begin(), |