diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2011-08-27 17:36:14 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2011-08-27 17:36:14 +0000 |
| commit | 2753ae314f656eab6d42c918469ce4ebf422cee5 (patch) | |
| tree | 0e0ee27a0435eba681fb8116871c0ac54f11a74d | |
| parent | f66f76c1a31539c65007a81fe28a1e06f638b4da (diff) | |
Silence GCC warnings and make an array const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 7 |
2 files changed, 6 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index a4ee032513..ccb84ab82c 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5216,7 +5216,7 @@ struct AddSubFlagsOpcodePair { unsigned MachineOpc; }; -static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { +static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { {ARM::ADCSri, ARM::ADCri}, {ARM::ADCSrr, ARM::ADCrr}, {ARM::ADCSrsi, ARM::ADCrsi}, @@ -5256,7 +5256,7 @@ bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI, // the tiny opcode table is not costly. static const int NPairs = sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair); - for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0], + for (const AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0], *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) { if (OldOpc == Pair->PseudoOpc) { NewOpc = Pair->MachineOpc; @@ -5303,7 +5303,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, Offset = -Offset; MachineMemOperand *MMO = *MI->memoperands_begin(); - MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)) + BuildMI(*BB, MI, dl, TII->get(NewOpc)) .addOperand(MI->getOperand(0)) // Rn_wb .addOperand(MI->getOperand(1)) // Rt .addOperand(MI->getOperand(2)) // Rn diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 98181b580e..9c940c49ca 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -10345,9 +10345,8 @@ static void ReplaceATOMIC_LOAD(SDNode *Node, // FIXME: On 32-bit, load -> fild or movq would be more efficient // (The only way to get a 16-byte load is cmpxchg16b) // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. - SDValue Zero = DAG.getConstant(0, cast<AtomicSDNode>(Node)->getMemoryVT()); - SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, - cast<AtomicSDNode>(Node)->getMemoryVT(), + SDValue Zero = DAG.getConstant(0, VT); + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, Node->getOperand(0), Node->getOperand(1), Zero, Zero, cast<AtomicSDNode>(Node)->getMemOperand(), @@ -10425,7 +10424,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, } case ISD::ATOMIC_CMP_SWAP: { EVT T = N->getValueType(0); - assert (T == MVT::i64 || T == MVT::i128 && "can only expand cmpxchg pair"); + assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); bool Regs64bit = T == MVT::i128; EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; SDValue cpInL, cpInH; |