diff options
author | Bob Wilson <bob.wilson@apple.com> | 2010-11-01 18:31:39 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2010-11-01 18:31:39 +0000 |
commit | 24645a1a6d317acfc16303237704f32364fb2f0f (patch) | |
tree | 0767f6c6fa95f8764e2da59544ae5e58ec88fff6 | |
parent | 4845f990081d466ad193d90d1cd6f1d0eb910309 (diff) |
NEON does not support truncating vector stores. Radar 8598391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 | ||||
-rw-r--r-- | test/CodeGen/ARM/vmov.ll | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index d086093597..6503960de9 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -104,6 +104,10 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); + for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) + setTruncStoreAction(VT.getSimpleVT(), + (MVT::SimpleValueType)InnerVT, Expand); } setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index 4d654d771f..a86be32bd2 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -343,3 +343,13 @@ declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone + +; Truncating vector stores are not supported. The following should not crash. +; Radar 8598391. +define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind { +;CHECK: vmovn + %tmp1 = load <4 x i32>* %a, align 16 + %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> + store <4 x i16> %tmp2, <4 x i16>* %b, align 8 + ret void +} |