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author | Jim Grosbach <grosbach@apple.com> | 2011-09-06 23:09:19 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-09-06 23:09:19 +0000 |
commit | 218affc710a0165746ec21a3315c6cc68272cfd5 (patch) | |
tree | e8bac2f0000590fc173aa93f273ec8d6bdfa1cd7 | |
parent | aa833e53dc74db6cb6789ef7f05c620d28980983 (diff) |
ISB is HasDB, not just HasV7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index fbaea3a4bd..8a29eaf639 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -2803,7 +2803,7 @@ def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, "isb", "\t$opt", - []>, Requires<[IsThumb2, HasV7]> { + []>, Requires<[IsThumb2, HasDB]> { bits<4> opt; let Inst{31-4} = 0xf3bf8f6; let Inst{3-0} = opt; |