diff options
| author | Eric Christopher <echristo@apple.com> | 2012-05-07 06:25:10 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2012-05-07 06:25:10 +0000 |
| commit | 1d5a392e2cff41488e47e038231fb114ea0eb941 (patch) | |
| tree | c7a2d52e64e5fa38b05017c4ae59a9a27d148446 | |
| parent | 54412a789a35386e11612739dd3b30ab382e5127 (diff) | |
Add support for the 'c' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 14 | ||||
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 8 |
2 files changed, 20 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 910416fe5c..854cfabbd7 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -2999,13 +2999,15 @@ getConstraintType(const std::string &Constraint) const // unless generating MIPS16 code. // 'y' : Equivalent to r; retained for // backwards compatibility. - // 'f' : Floating Point registers. + // 'c' : A register suitable for use in an indirect + // jump. This will always be $25 for -mabicalls. if (Constraint.size() == 1) { switch (Constraint[0]) { default : break; case 'd': case 'y': case 'f': + case 'c': return C_RegisterClass; } } @@ -3039,6 +3041,10 @@ MipsTargetLowering::getSingleConstraintMatchWeight( if (type->isFloatTy()) weight = CW_Register; break; + case 'c': // $25 for indirect jumps + if (type->isIntegerTy()) + weight = CW_SpecificReg; + break; case 'I': // signed 16 bit immediate case 'J': // integer zero case 'K': // unsigned 16 bit immediate @@ -3078,6 +3084,12 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const return std::make_pair(0U, &Mips::FGR64RegClass); return std::make_pair(0U, &Mips::AFGR64RegClass); } + break; + case 'c': // register suitable for indirect jump + if (VT == MVT::i32) + return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); + assert(VT == MVT::i64 && "Unexpected type."); + return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); } } return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll index ac84d2a16e..aa186ecef9 100644 --- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -22,6 +22,12 @@ entry: ;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 ;CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind - + +; Now c with 1024: make sure register $25 is picked +; CHECK: #APP +; CHECK: addi $25,${{[0-9]+}},1024 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind + ret i32 0 } |