diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-02-27 23:03:55 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-02-27 23:03:55 +0000 |
| commit | 15991bf775234d4d5c25510fe8703b4751bd31d1 (patch) | |
| tree | 4f732fd5aa089624eb51366944d7e7f6e0db085e | |
| parent | 898218cc5edecea1275ee266b2cd13313ea6b67b (diff) | |
Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34701 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 445fb26fc0..2f51144e47 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -101,31 +101,31 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, let MethodBodies = [{ // FP is R11, R9 is available. static const unsigned ARM_GPR_AO_1[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, + ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::LR, ARM::R11 }; // FP is R11, R9 is not available. static const unsigned ARM_GPR_AO_2[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, + ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R10, ARM::LR, ARM::R11 }; // FP is R7, R9 is available. static const unsigned ARM_GPR_AO_3[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, + ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R4, ARM::R5, ARM::R6, ARM::R8, ARM::R9, ARM::R10,ARM::R11, ARM::LR, ARM::R7 }; // FP is R7, R9 is not available. static const unsigned ARM_GPR_AO_4[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, + ARM::R3, ARM::R2, ARM::R1, ARM::R0, ARM::R4, ARM::R5, ARM::R6, ARM::R8, ARM::R10,ARM::R11, ARM::LR, ARM::R7 }; // FP is R7, only low registers available. static const unsigned THUMB_GPR_AO[] = { - ARM::R0, ARM::R1, ARM::R2, + ARM::R2, ARM::R1, ARM::R0, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; GPRClass::iterator |