diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-02-03 03:07:37 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-02-03 03:07:37 +0000 |
| commit | 133d3100eafed975b92f0714a959be438edcb32a (patch) | |
| tree | 900dfb6d1163982d6185835beb442d2d7351b37f | |
| parent | 84e752a8129e7a02ee6e3c6d356a8fd68fbdf698 (diff) | |
isStoreToStackSlot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25925 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 18 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.h | 1 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.td | 4 |
3 files changed, 20 insertions, 3 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index c64fe3bee9..7089f52e48 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -61,3 +61,21 @@ AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { return 0; } +unsigned +AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { + switch (MI->getOpcode()) { + case Alpha::STL: + case Alpha::STQ: + case Alpha::STB: + case Alpha::STW: + case Alpha::STS: + case Alpha::STT: + if (MI->getOperand(1).isFrameIndex()) { + FrameIndex = MI->getOperand(1).getFrameIndex(); + return MI->getOperand(0).getReg(); + } + break; + } + return 0; +} + diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h index 5211e6fcf5..7eed9effbf 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.h +++ b/lib/Target/Alpha/AlphaInstrInfo.h @@ -37,6 +37,7 @@ public: unsigned &SrcReg, unsigned &DstReg) const; virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; }; } diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 1d86462cd5..26891bc171 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -177,9 +177,7 @@ def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST", [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))]>; -//FIXME: fold setcc with select for all cases. clearly I need patterns for inverted conditions -// and constants (which require inverted conditions as legalize puts the constant in the -// wrong field for the instruction definition +//General pattern for cmov def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2), (CMOVNE GPRC:$src2, GPRC:$src1, GPRC:$which)>; def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2), |