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| author | Evan Cheng <evan.cheng@apple.com> | 2011-12-14 02:28:53 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-12-14 02:28:53 +0000 |
| commit | 12dfdb424ddcfabb347f168f9332795ba443ccd3 (patch) | |
| tree | 94bf61e0a2e50579e0ebeb95a4a7c4ed02a0910e | |
| parent | dbdc616ed5eb1c92d75465333b0d96b0185f8c8f (diff) | |
Allow target to specify register output dependency. Still default to one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 10 | ||||
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 8 |
2 files changed, 17 insertions, 1 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 1903da73e6..957a89af82 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -648,6 +648,16 @@ public: SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const; + /// getOutputLatency - Compute and return the output dependency latency of a + /// a given pair of defs which both target the same register. This is usually + /// one. + virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, + const MachineInstr *DefMI1, + const MachineInstr *DefMI2, + unsigned Reg) const { + return 1; + } + /// getInstrLatency - Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via /// PredCost. diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index aedc2a13fa..47c533932d 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -278,7 +278,13 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) { if (DefSU != SU && (Kind != SDep::Output || !MO.isDead() || !DefSU->getInstr()->registerDefIsDead(Reg))) { - DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg)); + if (Kind == SDep::Anti) + DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg)); + else { + unsigned AOLat = TII->getOutputLatency(InstrItins, MI, + DefSU->getInstr(), Reg); + DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg)); + } } } for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { |