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| author | Evan Cheng <evan.cheng@apple.com> | 2007-06-29 00:01:20 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-06-29 00:01:20 +0000 |
| commit | 0db5862cb88523b8ea2daf7e93650ec04bf6c1d5 (patch) | |
| tree | c8c1bdcf70a169f07a58238efb825fe6c24d4789 | |
| parent | 890e1a040155e8b69d258bc18ba7f0769c7c989a (diff) | |
Type of vector extract / insert index operand should be iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37784 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4c1d6ea406..f9c19bc0f0 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -2959,7 +2959,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { if (N1.getValueType() != MVT::i32) N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); if (N2.getValueType() != MVT::i32) - N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32); + N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy()); return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); } else if (MVT::getSizeInBits(BaseVT) == 32) { unsigned Idx = cast<ConstantSDNode>(N2)->getValue(); |