diff options
| author | Bill Wendling <isanbard@gmail.com> | 2010-12-03 00:53:22 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-12-03 00:53:22 +0000 |
| commit | 0bdf0c05b990b4f2d29719b34f4ce44f16176f09 (patch) | |
| tree | fe066b81bb268868f65828bf8d4bea27674e86b4 | |
| parent | b0d98692a68cf7d5a8fce6115d8bf918126177a8 (diff) | |
The tLDR instruction wasn't encoded properly:
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>
Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 4b059197ff..d6926d9450 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -642,8 +642,12 @@ static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx, const MCOperand &MO2 = MI.getOperand(OpIdx + 2); unsigned Rn = getARMRegisterNumbering(MO.getReg()); unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f; - unsigned Rm = getARMRegisterNumbering(MO2.getReg()); - return (Rm << 3) | (Imm5 << 3) | Rn; + + if (MO2.getReg() != 0) + // Is an immediate. + Imm5 = getARMRegisterNumbering(MO2.getReg()); + + return (Imm5 << 3) | Rn; } /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands. |