diff options
| author | Devang Patel <dpatel@apple.com> | 2011-04-22 16:44:29 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2011-04-22 16:44:29 +0000 |
| commit | 0a6ea83f393d06fb424c470777a1c3e8a8c50ab1 (patch) | |
| tree | 4a433881293d357bb30167f27f8b44bcd14eac8d | |
| parent | b20a8fc8a6bf57dbde0e9238cf535abb4326dc80 (diff) | |
Add asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMAsmPrinter.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 47a6520629..b8c117c2cb 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -180,6 +180,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const { else { unsigned Reg = MLoc.getReg(); if (Reg >= ARM::S0 && Reg <= ARM::S31) { + assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering"); // S registers are described as bit-pieces of a register // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0) // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32) @@ -210,6 +211,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const { EmitULEB128(0); } } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) { + assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering"); // Q registers Q0-Q15 are described by composing two D registers together. // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8) |