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| author | Eric Christopher <echristo@apple.com> | 2011-06-30 01:05:46 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2011-06-30 01:05:46 +0000 |
| commit | 0a1509e779d3f97bb1df68c9e63c41ff5b66441d (patch) | |
| tree | 9e52dc52cc4fcbaa777167b5e9258e9d77b9fedb | |
| parent | 5d8aa345dd8f92d572a3c639ee7c6f5a7a932384 (diff) | |
Make sure we use the correct register class here since we'll need to
care about spill values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134122 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 54433a4c36..daf9555189 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -835,7 +835,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'r': return std::make_pair(0U, Alpha::GPRCRegisterClass); case 'f': - return std::make_pair(0U, Alpha::F4RCRegisterClass); + return VT == MVT::f64 ? std::make_pair(0U, Alpha::F8RCRegisterClass) : + std::make_pair(0U, Alpha::F4RCRegisterClass); } } return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); |