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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-01-14 18:19:56 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-01-14 18:19:56 +0000 |
| commit | 09bf003983bb35190ce9932c4edc9a7635f379c0 (patch) | |
| tree | 018cecb86d85cbe4261885666e0c03bcb415a987 | |
| parent | dfe7281fab2f209fa2015b5a21ea142bcc1ef457 (diff) | |
ARM "l" constraint for inline asm means R0-R7, also for Thumb2.
This is consistent with llvm-gcc's arm/constraints.md.
Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93436 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 6643b74dd0..275b30c9ae 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4258,10 +4258,10 @@ std::pair<unsigned, const TargetRegisterClass*> ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { if (Constraint.size() == 1) { - // GCC RS6000 Constraint Letters + // GCC ARM Constraint Letters switch (Constraint[0]) { case 'l': - if (Subtarget->isThumb1Only()) + if (Subtarget->isThumb()) return std::make_pair(0U, ARM::tGPRRegisterClass); else return std::make_pair(0U, ARM::GPRRegisterClass); |