diff options
| author | Jan Sjödin <jan_sjodin@yahoo.com> | 2011-12-02 15:14:37 +0000 |
|---|---|---|
| committer | Jan Sjödin <jan_sjodin@yahoo.com> | 2011-12-02 15:14:37 +0000 |
| commit | ce25d26b400d25c9e20ac9fe2d5b0cafb9d7fa15 (patch) | |
| tree | e4dcaeca66d1bf96d7a5fe7afe640e467a386d60 | |
| parent | f8363305ebd026fafda41491fc7df3b22d58f968 (diff) | |
Add XOP feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86.td | 7 | ||||
| -rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/X86/X86Subtarget.h | 4 |
3 files changed, 12 insertions, 2 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index aa92f084ff..8229ca5444 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -91,6 +91,8 @@ def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", "Enable three-operand fused multiple-add">; def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", "Enable four-operand fused multiple-add">; +def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", + "Enable XOP instructions">; def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", "HasVectorUAMem", "true", "Allow unaligned memory operands on vector/SIMD instructions">; @@ -199,10 +201,11 @@ def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A, // FIXME: Disabling AVX for now since it's not ready. def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B, FeatureAES, FeatureCLMUL, FeatureFMA4, - FeatureLZCNT]>; + FeatureXOP, FeatureLZCNT]>; def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B, FeatureAES, FeatureCLMUL, FeatureFMA4, - FeatureF16C, FeatureLZCNT, FeatureBMI]>; + FeatureXOP, FeatureF16C, FeatureLZCNT, + FeatureBMI]>; def : Proc<"winchip-c6", [FeatureMMX]>; def : Proc<"winchip2", [Feature3DNow]>; diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index e7bcbf898b..d7fa8ca574 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -273,6 +273,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() { if (IsAMD && ((ECX >> 16) & 0x1)) { HasFMA4 = true; ToggleFeature(X86::FeatureFMA4); + HasXOP = true; + ToggleFeature(X86::FeatureXOP); } } } @@ -317,6 +319,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, , HasCLMUL(false) , HasFMA3(false) , HasFMA4(false) + , HasXOP(false) , HasMOVBE(false) , HasRDRAND(false) , HasF16C(false) diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index e93f8e94f6..ccb9be0c97 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -93,6 +93,9 @@ protected: /// HasFMA4 - Target has 4-operand fused multiply-add bool HasFMA4; + /// HasXOP - Target has XOP instructions + bool HasXOP; + /// HasMOVBE - True if the processor has the MOVBE instruction. bool HasMOVBE; @@ -198,6 +201,7 @@ public: bool hasCLMUL() const { return HasCLMUL; } bool hasFMA3() const { return HasFMA3; } bool hasFMA4() const { return HasFMA4; } + bool hasXOP() const { return HasXOP; } bool hasMOVBE() const { return HasMOVBE; } bool hasRDRAND() const { return HasRDRAND; } bool hasF16C() const { return HasF16C; } |