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| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-01 06:53:52 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-01 06:53:52 +0000 |
| commit | acf7f2e3a9ade9660caad082be1e3b37bafd7f18 (patch) | |
| tree | 1ad35ff78b482f6ad108dd8663fc4a3c660db3f8 | |
| parent | a90a24c623822c4612f054d6e90091ca02fdde5f (diff) | |
Fix ldmxcsr JIT encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31343 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 7361c70cdf..f7b8d61428 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1653,12 +1653,10 @@ def MFENCE : I<0xAE, MRM6m, (ops), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>; // MXCSR register -def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src), - "ldmxcsr $src", - [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>; -def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst), - "stmxcsr $dst", - [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>; +def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src), + "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>; +def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst), + "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>; // Thread synchronization def MONITOR : I<0xC8, RawFrm, (ops), "monitor", |