Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 34 insertions, 72 deletions

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index bc486066d2..22461c4330 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -805,13 +805,13 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
   }
 
   case ARM::MOVi32imm:
-    emitMOVi32immInstruction(MI);
-    break;
-
-  case ARM::MOVi2pieces:
     // Two instructions to materialize a constant.
-    emitMOVi2piecesInstruction(MI);
+    if (Subtarget->hasV6T2Ops())
+      emitMOVi32immInstruction(MI);
+    else
+      emitMOVi2piecesInstruction(MI);
     break;
+
   case ARM::LEApcrelJT:
     // Materialize jumptable address.
     emitLEApcrelJTInstruction(MI);
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 4c556479d1..b252fd248b 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -36,6 +36,7 @@ namespace {
 
     const ARMBaseInstrInfo *TII;
     const TargetRegisterInfo *TRI;
+    const ARMSubtarget *STI;
 
     virtual bool runOnMachineFunction(MachineFunction &Fn);
 
@@ -698,6 +699,28 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
       const MachineOperand &MO = MI.getOperand(1);
       MachineInstrBuilder LO16, HI16;
 
+      if (Opcode == ARM::MOVi32imm && !STI->hasV6T2Ops()) {
+        // Expand into a movi + orr.
+        LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
+        HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
+          .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+          .addReg(DstReg);
+
+        assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
+        unsigned ImmVal = (unsigned)MO.getImm();
+        unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
+        unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
+        LO16 = LO16.addImm(SOImmValV1);
+        HI16 = HI16.addImm(SOImmValV2);
+        (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+        (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+        LO16.addImm(Pred).addReg(PredReg).addReg(0);
+        HI16.addImm(Pred).addReg(PredReg).addReg(0);
+        TransferImpOps(MI, LO16, HI16);
+        MI.eraseFromParent();
+        break;
+      }
+
       LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
                      TII->get(Opcode == ARM::MOVi32imm ?
                               ARM::MOVi16 : ARM::t2MOVi16),
@@ -729,34 +752,6 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
       break;
     }
 
-    case ARM::MOVi2pieces: {
-      unsigned PredReg = 0;
-      ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
-      unsigned DstReg = MI.getOperand(0).getReg();
-      bool DstIsDead = MI.getOperand(0).isDead();
-      const MachineOperand &MO = MI.getOperand(1);
-      MachineInstrBuilder LO16, HI16;
-
-      LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
-      HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
-        .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-        .addReg(DstReg);
-
-      assert (MO.isImm() && "MOVi2pieces w/ non-immediate source operand!");
-      unsigned ImmVal = (unsigned)MO.getImm();
-      unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
-      unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
-      LO16 = LO16.addImm(SOImmValV1);
-      HI16 = HI16.addImm(SOImmValV2);
-      (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
-      (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
-      LO16.addImm(Pred).addReg(PredReg).addReg(0);
-      HI16.addImm(Pred).addReg(PredReg).addReg(0);
-      TransferImpOps(MI, LO16, HI16);
-      MI.eraseFromParent();
-      break;
-    }
-
     case ARM::VMOVQQ: {
       unsigned DstReg = MI.getOperand(0).getReg();
       bool DstIsDead = MI.getOperand(0).isDead();
@@ -1060,6 +1055,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
   TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
   TRI = MF.getTarget().getRegisterInfo();
+  STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
 
   bool Modified = false;
   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index f6c2df2758..6f48d967f9 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -59,27 +59,3 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
 
   return 0;
 }
-
-void ARMInstrInfo::
-reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-              unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
-              const TargetRegisterInfo &TRI) const {
-  DebugLoc dl = Orig->getDebugLoc();
-  unsigned Opcode = Orig->getOpcode();
-  switch (Opcode) {
-  default:
-    break;
-  case ARM::MOVi2pieces: {
-    RI.emitLoadConstPool(MBB, I, dl,
-                         DestReg, SubIdx,
-                         Orig->getOperand(1).getImm(),
-                         ARMCC::AL, 0); // Pre-if-conversion, so default pred.
-    MachineInstr *NewMI = prior(I);
-    NewMI->getOperand(0).setSubReg(SubIdx);
-    return;
-  }
-  }
-
-  return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
-}
-
diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 4563ffea7b..f2c7bdc31b 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -32,11 +32,6 @@ public:
   // if there is not such an opcode.
   unsigned getUnindexedOpcode(unsigned Opc) const;
 
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, unsigned SubIdx,
-                     const MachineInstr *Orig,
-                     const TargetRegisterInfo &TRI) const;
-
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 849bda8f0c..95106218b3 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3201,14 +3201,9 @@ def Int_eh_sjlj_dispatchsetup :
 
 // Large immediate handling.
 
-// Two piece so_imms.
-// FIXME: Remove this when we can do generalized remat.
-let isReMaterializable = 1 in
-def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
-                             IIC_iMOVix2, "",
-                             [(set GPR:$dst, (so_imm2part:$src))]>,
-                  Requires<[IsARM, NoV6T2]>;
-
+// FIXME: Folding immediates into these logical operations aren't necessary
+// good ideas. If it's in a loop machine licm could have hoisted the immediate
+// computation out of the loop.
 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
              (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
                     (so_imm2part_2 imm:$RHS))>;
@@ -3222,14 +3217,14 @@ def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
              (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
                     (so_neg_imm2part_2 imm:$RHS))>;
 
-// 32-bit immediate using movw + movt.
+// 32-bit immediate using two piece so_imms or movw + movt.
 // This is a single pseudo instruction, the benefit is that it can be remat'd
 // as a single unit instead of having to handle reg inputs.
 // FIXME: Remove this when we can do generalized remat.
 let isReMaterializable = 1 in
 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
                            [(set GPR:$dst, (i32 imm:$src))]>,
-                           Requires<[IsARM, HasV6T2]>;
+                           Requires<[IsARM]>;
 
 // ConstantPool, GlobalAddress, and JumpTable
 def : ARMPat<(ARMWrapper  tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,