diff options
| author | Manman Ren <mren@apple.com> | 2012-06-14 05:57:42 +0000 |
|---|---|---|
| committer | Manman Ren <mren@apple.com> | 2012-06-14 05:57:42 +0000 |
| commit | 7a0575b9a8ca291c33495623eae171394f33b58f (patch) | |
| tree | 3eda454b3469b1d78aab393603cbf8b2b5f35b59 | |
| parent | ce5c6fb55f089cb92c99bf172c9c550e69dcb6c7 (diff) | |
InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).
uno && ueq was converted to ueq, it should be converted to uno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158441 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/ARM/iabs.ll | 20 | ||||
| -rw-r--r-- | test/Transforms/InstCombine/and-fcmp.ll | 11 |
3 files changed, 34 insertions, 3 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 3bafc6661b..7d0af0d802 100644 --- a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -995,9 +995,11 @@ Value *InstCombiner::FoldAndOfFCmps(FCmpInst *LHS, FCmpInst *RHS) { std::swap(Op0Ordered, Op1Ordered); } if (Op0Pred == 0) { - // uno && ueq -> uno && (uno || eq) -> ueq + // uno && ueq -> uno && (uno || eq) -> uno // ord && olt -> ord && (ord && lt) -> olt - if (Op0Ordered == Op1Ordered) + if (!Op0Ordered && (Op0Ordered == Op1Ordered)) + return LHS; + if (Op0Ordered && (Op0Ordered == Op1Ordered)) return RHS; // uno && oeq -> uno && (ord && eq) -> false diff --git a/test/CodeGen/ARM/iabs.ll b/test/CodeGen/ARM/iabs.ll index 89e309d160..e7026791c9 100644 --- a/test/CodeGen/ARM/iabs.ll +++ b/test/CodeGen/ARM/iabs.ll @@ -10,7 +10,25 @@ define i32 @test(i32 %a) { %b = icmp sgt i32 %a, -1 %abs = select i1 %b, i32 %a, i32 %tmp1neg ret i32 %abs -; CHECK: movs r0, r0 +; CHECK: cmp ; CHECK: rsbmi r0, r0, #0 ; CHECK: bx lr } + +; rdar://11633193 +; 3 instructions will be generated for the following case: +; subs +; rsbmi +; bx +define i32 @test2(i32 %a, i32 %b) nounwind readnone ssp { +entry: +; CHECK: test2 +; CHECK-NEXT: subs +; CHECK-NEXT: rsbmi +; CHECK-NEXT: bx + %sub = sub nsw i32 %a, %b + %cmp = icmp sgt i32 %sub, -1 + %sub1 = sub nsw i32 0, %sub + %cond = select i1 %cmp, i32 %sub, i32 %sub1 + ret i32 %cond +} diff --git a/test/Transforms/InstCombine/and-fcmp.ll b/test/Transforms/InstCombine/and-fcmp.ll index 282e88b53d..838c2f73fb 100644 --- a/test/Transforms/InstCombine/and-fcmp.ll +++ b/test/Transforms/InstCombine/and-fcmp.ll @@ -66,3 +66,14 @@ define zeroext i8 @t6(float %x, float %y) nounwind { ; CHECK: t6 ; CHECK: ret i8 0 } + +define zeroext i8 @t7(float %x, float %y) nounwind { + %a = fcmp uno float %x, %y + %b = fcmp ult float %x, %y + %c = and i1 %a, %b + %retval = zext i1 %c to i8 + ret i8 %retval +; CHECK: t7 +; CHECK: fcmp uno +; CHECK-NOT: fcmp ult +} |