diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
| commit | 64d80e3387f328d21cd9cc06464b5de7861e3f27 (patch) | |
| tree | 203a9dfb41eba2fd8bd65a1e8bb80f73e36c0771 | |
| parent | 4558b807a2076e199bcb019f5edc9eabbc5922c1 (diff) | |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
33 files changed, 2664 insertions, 2514 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index adc203b6e9..c984ee1e5f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -362,63 +362,72 @@ class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im, let Constraints = cstr; } -class PseudoInst<dag ops, string asm, list<dag> pattern> +class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> { - let OperandList = ops; + let OutOperandList = oops; + let InOperandList = iops; let AsmString = asm; let Pattern = pattern; } // Almost all ARM instructions are predicable. -class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im, +class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, string opc, string asm, string cstr, list<dag> pattern> // FIXME: Set all opcodes to 0 for now. : InstARM<0, am, sz, im, cstr> { - let OperandList = !con(oprnds, (ops pred:$p)); + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p)); let AsmString = !strconcat(opc, !strconcat("${p}", asm)); let Pattern = pattern; list<Predicate> Predicates = [IsARM]; } -// Same as I except it can optionally modify CPSR. -class sI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im, +// Same as I except it can optionally modify CPSR. Note it's modeled as +// an input operand since by default it's a zero register. It will +// become an implicit def once it's "flipped". +class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, string opc, string asm, string cstr, list<dag> pattern> // FIXME: Set all opcodes to 0 for now. : InstARM<0, am, sz, im, cstr> { - let OperandList = !con(oprnds, (ops pred:$p, cc_out:$s)); + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); let Pattern = pattern; list<Predicate> Predicates = [IsARM]; } -class AI<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AsI<dag ops, string opc, string asm, list<dag> pattern> - : sI<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AI1<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AsI1<dag ops, string opc, string asm, list<dag> pattern> - : sI<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AI2<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AI3<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AI4<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; -class AI1x2<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>; +class AI<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm,"",pattern>; +class AsI<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc,asm,"",pattern>; +class AI1<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; +class AsI1<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; +class AI2<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; +class AI3<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; +class AI4<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>; +class AI1x2<dag oops, dag iops, string opc, string asm, list<dag> pattern> + : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>; // Pre-indexed ops -class AI2pr<dag ops, string opc, string asm, string cstr, list<dag> pattern> - : I<ops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>; -class AI3pr<dag ops, string opc, string asm, string cstr, list<dag> pattern> - : I<ops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>; +class AI2pr<dag oops, dag iops, string opc, string asm, string cstr, + list<dag> pattern> + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>; +class AI3pr<dag oops, dag iops, string opc, string asm, string cstr, + list<dag> pattern> + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>; // Post-indexed ops -class AI2po<dag ops, string opc, string asm, string cstr, list<dag> pattern> - : I<ops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>; -class AI3po<dag ops, string opc, string asm, string cstr, list<dag> pattern> - : I<ops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>; +class AI2po<dag oops, dag iops, string opc, string asm, string cstr, + list<dag> pattern> + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>; +class AI3po<dag oops, dag iops, string opc, string asm, string cstr, + list<dag> pattern> + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>; class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; @@ -428,13 +437,13 @@ class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a /// binop that produces a value. multiclass AsI1_bin_irs<string opc, PatFrag opnode> { - def ri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b), + def ri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b), opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; - def rr : AsI1<(ops GPR:$dst, GPR:$a, GPR:$b), + def rr : AsI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b), opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; - def rs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b), + def rs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b), opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; } @@ -442,13 +451,13 @@ multiclass AsI1_bin_irs<string opc, PatFrag opnode> { /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the /// instruction modifies the CSPR register. multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> { - def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), + def ri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b), opc, "s $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>; - def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b), + def rr : AI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b), opc, "s $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>; - def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), + def rs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b), opc, "s $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>; } @@ -457,13 +466,13 @@ multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> { /// patterns. Similar to AsI1_bin_irs except the instruction does not produce /// a explicit result, only implicitly set CPSR. multiclass AI1_cmp_irs<string opc, PatFrag opnode> { - def ri : AI1<(ops GPR:$a, so_imm:$b), + def ri : AI1<(outs), (ins GPR:$a, so_imm:$b), opc, " $a, $b", [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>; - def rr : AI1<(ops GPR:$a, GPR:$b), + def rr : AI1<(outs), (ins GPR:$a, GPR:$b), opc, " $a, $b", [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>; - def rs : AI1<(ops GPR:$a, so_reg:$b), + def rs : AI1<(outs), (ins GPR:$a, so_reg:$b), opc, " $a, $b", [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>; } @@ -471,10 +480,10 @@ multiclass AI1_cmp_irs<string opc, PatFrag opnode> { /// AI_unary_rrot - A unary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. multiclass AI_unary_rrot<string opc, PatFrag opnode> { - def r : AI<(ops GPR:$dst, GPR:$Src), + def r : AI<(outs GPR:$dst), (ins GPR:$Src), opc, " $dst, $Src", [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>; - def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot), + def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), opc, " $dst, $Src, ror $rot", [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, Requires<[IsARM, HasV6]>; @@ -483,11 +492,11 @@ multiclass AI_unary_rrot<string opc, PatFrag opnode> { /// AI_bin_rrot - A binary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. multiclass AI_bin_rrot<string opc, PatFrag opnode> { - def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS), + def rr : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), opc, " $dst, $LHS, $RHS", [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, Requires<[IsARM, HasV6]>; - def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot), + def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), opc, " $dst, $LHS, $RHS, ror $rot", [(set GPR:$dst, (opnode GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)))]>, @@ -495,48 +504,49 @@ multiclass AI_bin_rrot<string opc, PatFrag opnode> { } // Special cases. -class XI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im, +class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, string asm, string cstr, list<dag> pattern> // FIXME: Set all opcodes to 0 for now. : InstARM<0, am, sz, im, cstr> { - let OperandList = oprnds; + let OutOperandList = oops; + let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list<Predicate> Predicates = [IsARM]; } -class AXI<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>; -class AXI1<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>; -class AXI2<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>; -class AXI3<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>; -class AXI4<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>; +class AXI<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>; +class AXI1<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>; +class AXI2<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>; +class AXI3<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>; +class AXI4<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>; -class AXIx2<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>; +class AXIx2<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>; // BR_JT instructions -class JTI<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>; -class JTI1<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>; -class JTI2<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>; +class JTI<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>; +class JTI1<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>; +class JTI2<dag oops, dag iops, string asm, list<dag> pattern> + : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>; /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and /// setting carry bit. But it can optionally set CPSR. multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> { - def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s), + def ri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), !strconcat(opc, "${s} $dst, $a, $b"), [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>; - def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b, cc_out:$s), + def rr : AXI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s), !strconcat(opc, "${s} $dst, $a, $b"), [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>; - def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s), + def rs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), !strconcat(opc, "${s} $dst, $a, $b"), [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>; } @@ -549,7 +559,7 @@ multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> { // Miscellaneous Instructions. // def IMPLICIT_DEF_GPR : -PseudoInst<(ops GPR:$rD, pred:$p), +PseudoInst<(outs GPR:$rD), (ins pred:$p), "@ IMPLICIT_DEF_GPR $rD", [(set GPR:$rD, (undef))]>; @@ -560,68 +570,69 @@ PseudoInst<(ops GPR:$rD, pred:$p), /// size in bytes of this constant pool entry. let isNotDuplicable = 1 in def CONSTPOOL_ENTRY : -PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), +PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, + i32imm:$size), "${instid:label} ${cpidx:cpentry}", []>; def ADJCALLSTACKUP : -PseudoInst<(ops i32imm:$amt, pred:$p), +PseudoInst<(outs), (ins i32imm:$amt, pred:$p), "@ ADJCALLSTACKUP $amt", [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>; def ADJCALLSTACKDOWN : -PseudoInst<(ops i32imm:$amt, pred:$p), +PseudoInst<(outs), (ins i32imm:$amt, pred:$p), "@ ADJCALLSTACKDOWN $amt", [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>; def DWARF_LOC : -PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file), +PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), ".loc $file, $line, $col", [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; let isNotDuplicable = 1 in { -def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p), +def PICADD : AXI1<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), "$cp:\n\tadd$p $dst, pc, $a", [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; let isLoad = 1, AddedComplexity = 10 in { -def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLD : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; -def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDZH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; -def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDZB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; -def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}h $dst, $addr", [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>; -def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}b $dst, $addr", [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>; -def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDSH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; -def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDSB : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; } let isStore = 1, AddedComplexity = 10 in { -def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), +def PICSTR : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tstr$p $src, $addr", [(store GPR:$src, addrmodepc:$addr)]>; -def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p), +def PICSTRH : AXI3<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tstr${p}h $src, $addr", [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; -def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), +def PICSTRB : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tstr${p}b $src, $addr", [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; } @@ -632,34 +643,37 @@ def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), // let isReturn = 1, isTerminator = 1 in - def BX_RET : AI<(ops), "bx", " lr", [(ARMretflag)]>; + def BX_RET : AI<(outs), (ins), "bx", " lr", [(ARMretflag)]>; // FIXME: remove when we have a way to marking a MI with these properties. +// FIXME: $dst1 should be a def. But the extra ops must be in the end of the +// operand list. let isLoad = 1, isReturn = 1, isTerminator = 1 in - def LDM_RET : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), + def LDM_RET : AXI4<(outs), + (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), "ldm${p}${addr:submode} $addr, $dst1", []>; let isCall = 1, noResults = 1, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { - def BL : AXI<(ops i32imm:$func, variable_ops), + def BL : AXI<(outs), (ins i32imm:$func, variable_ops), "bl ${func:call}", [(ARMcall tglobaladdr:$func)]>; - def BL_pred : AI<(ops i32imm:$func, variable_ops), + def BL_pred : AI<(outs), (ins i32imm:$func, variable_ops), "bl", " ${func:call}", [(ARMcall_pred tglobaladdr:$func)]>; // ARMv5T and above - def BLX : AXI<(ops GPR:$dst, variable_ops), - "blx $dst", - [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>; + def BLX : AXI<(outs), (ins GPR:$func, variable_ops), + "blx $func", + [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>; let Uses = [LR] in { // ARMv4T - def BX : AXIx2<(ops GPR:$dst, variable_ops), - "mov lr, pc\n\tbx $dst", - [(ARMcall_nolink GPR:$dst)]>; + def BX : AXIx2<(outs), (ins GPR:$func, variable_ops), + "mov lr, pc\n\tbx $func", + [(ARMcall_nolink GPR:$func)]>; } } @@ -667,28 +681,29 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in { // B is "predicable" since it can be xformed into a Bcc. let isBarrier = 1 in { let isPredicable = 1 in - def B : AXI<(ops brtarget:$dst), "b $dst", - [(br bb:$dst)]>; + def B : AXI<(outs), (ins brtarget:$target), "b $target", + [(br bb:$target)]>; let isNotDuplicable = 1 in { - def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id), - "mov pc, $dst \n$jt", - [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>; - def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id), - "ldr pc, $dst \n$jt", - [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt, + def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), + "mov pc, $target \n$jt", + [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; + def BR_JTm : JTI2<(outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), + "ldr pc, $target \n$jt", + [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, imm:$id)]>; - def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id), - "add pc, $dst, $idx \n$jt", - [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt, + def BR_JTadd : JTI1<(outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, + i32imm:$id), + "add pc, $target, $idx \n$jt", + [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>; } } // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node expects two operands. :( - def Bcc : AI<(ops brtarget:$dst), "b", " $dst", - [/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>; + def Bcc : AI<(outs), (ins brtarget:$target), "b", " $target", + [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; } //===----------------------------------------------------------------------===// @@ -697,117 +712,123 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in { // Load let isLoad = 1 in { -def LDR : AI2<(ops GPR:$dst, addrmode2:$addr), +def LDR : AI2<(outs GPR:$dst), (ins addrmode2:$addr), "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. let isReMaterializable = 1 in -def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr), +def LDRcp : AI2<(outs GPR:$dst), (ins addrmode2:$addr), "ldr", " $dst, $addr", []>; // Loads with zero extension -def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr), +def LDRH : AI3<(outs GPR:$dst), (ins addrmode3:$addr), "ldr", "h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; -def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr), +def LDRB : AI2<(outs GPR:$dst), (ins addrmode2:$addr), "ldr", "b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; // Loads with sign extension -def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr), +def LDRSH : AI3<(outs GPR:$dst), (ins addrmode3:$addr), "ldr", "sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; -def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr), +def LDRSB : AI3<(outs GPR:$dst), (ins addrmode3:$addr), "ldr", "sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; // Load doubleword -def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr), +def LDRD : AI3<(outs GPR:$dst), (ins addrmode3:$addr), "ldr", "d $dst, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed loads -def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr), +def LDR_PRE : AI2pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode2:$addr), "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; -def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset), +def LDR_POST : AI2po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base, am2offset:$offset), "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), +def LDRH_PRE : AI3pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode3:$addr), "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), +def LDRH_POST : AI3po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am3offset:$offset), "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr), +def LDRB_PRE : AI2pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode2:$addr), "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset), +def LDRB_POST : AI2po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am2offset:$offset), "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), +def LDRSH_PRE : AI3pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode3:$addr), "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), +def LDRSH_POST: AI3po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am3offset:$offset), "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), +def LDRSB_PRE : AI3pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode3:$addr), "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), +def LDRSB_POST: AI3po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am3offset:$offset), "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; } // isLoad // Store let isStore = 1 in { -def STR : AI2<(ops GPR:$src, addrmode2:$addr), +def STR : AI2<(outs), (ins GPR:$src, addrmode2:$addr), "str", " $src, $addr", [(store GPR:$src, addrmode2:$addr)]>; // Stores with truncate -def STRH : AI3<(ops GPR:$src, addrmode3:$addr), +def STRH : AI3<(outs), (ins GPR:$src, addrmode3:$addr), "str", "h $src, $addr", [(truncstorei16 GPR:$src, addrmode3:$addr)]>; -def STRB : AI2<(ops GPR:$src, addrmode2:$addr), +def STRB : AI2<(outs), (ins GPR:$src, addrmode2:$addr), "str", "b $src, $addr", [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword -def STRD : AI3<(ops GPR:$src, addrmode3:$addr), +def STRD : AI3<(outs), (ins GPR:$src, addrmode3:$addr), "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed stores -def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset), +def STR_PRE : AI2pr<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base, am2offset:$offset), "str", " $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; -def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), +def STR_POST : AI2po<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), "str", " $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; -def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset), +def STRH_PRE : AI3pr<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am3offset:$offset), "str", "h $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; -def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset), +def STRH_POST: AI3po<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am3offset:$offset), "str", "h $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti16 GPR:$src, GPR:$base, am3offset:$offset))]>; -def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), +def STRB_PRE : AI2pr<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), "str", "b $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; -def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), +def STRB_POST: AI2po<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), "str", "b $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; @@ -817,13 +838,16 @@ def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), // Load / store multiple Instructions. // +// FIXME: $dst1 should be a def. let isLoad = 1 in -def LDM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), +def LDM : AXI4<(outs), + (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), "ldm${p}${addr:submode} $addr, $dst1", []>; let isStore = 1 in -def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), +def STM : AXI4<(outs), + (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), "stm${p}${addr:submode} $addr, $src1", []>; @@ -831,26 +855,26 @@ def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), // Move Instructions. // -def MOVr : AsI1<(ops GPR:$dst, GPR:$src), +def MOVr : AsI1<(outs GPR:$dst), (ins GPR:$src), "mov", " $dst, $src", []>; -def MOVs : AsI1<(ops GPR:$dst, so_reg:$src), +def MOVs : AsI1<(outs GPR:$dst), (ins so_reg:$src), "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>; let isReMaterializable = 1 in -def MOVi : AsI1<(ops GPR:$dst, so_imm:$src), +def MOVi : AsI1<(outs GPR:$dst), (ins so_imm:$src), "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>; -def MOVrx : AsI1<(ops GPR:$dst, GPR:$src), - "mov", " $dst, $src, rrx", - [(set GPR:$dst, (ARMrrx GPR:$src))]>; +def MOVrx : AsI1<(outs GPR:$dst), (ins GPR:$src), + "mov", " $dst, $src, rrx", + [(set GPR:$dst, (ARMrrx GPR:$src))]>; // These aren't really mov instructions, but we have to define them this way // due to flag operands. -def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src), +def MOVsrl_flag : AI1<(outs GPR:$dst), (ins GPR:$src), "mov", "s $dst, $src, lsr #1", [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>; -def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src), +def MOVsra_flag : AI1<(outs GPR:$dst), (ins GPR:$src), "mov", "s $dst, $src, asr #1", [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>; @@ -909,27 +933,27 @@ defm ADC : AsXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; defm SBC : AsXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; // These don't define reg/reg forms, because they are handled above. -def RSBri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b), +def RSBri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b), "rsb", " $dst, $a, $b", [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; -def RSBrs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b), +def RSBrs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b), "rsb", " $dst, $a, $b", [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; // RSB with 's' bit set. -def RSBSri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), +def RSBSri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b), "rsb", "s $dst, $a, $b", [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>; -def RSBSrs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), +def RSBSrs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b), "rsb", "s $dst, $a, $b", [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>; // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. -def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s), +def RSCri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), "rsc${s} $dst, $a, $b", [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>; -def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s), +def RSCrs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), "rsc${s} $dst, $a, $b", [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>; @@ -958,12 +982,12 @@ defm ORR : AsI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; defm EOR : AsI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; defm BIC : AsI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; -def MVNr : AsI<(ops GPR:$dst, GPR:$src), +def MVNr : AsI<(outs GPR:$dst), (ins GPR:$src), "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; -def MVNs : AsI<(ops GPR:$dst, so_reg:$src), +def MVNs : AsI<(outs GPR:$dst), (ins so_reg:$src), "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; let isReMaterializable = 1 in -def MVNi : AsI<(ops GPR:$dst, so_imm:$imm), +def MVNi : AsI<(outs GPR:$dst), (ins so_imm:$imm), "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; def : ARMPat<(and GPR:$src, so_imm_not:$imm), @@ -973,76 +997,76 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm), // Multiply Instructions. // -def MUL : AsI<(ops GPR:$dst, GPR:$a, GPR:$b), +def MUL : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), "mul", " $dst, $a, $b", [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; -def MLA : AsI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), +def MLA : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), "mla", " $dst, $a, $b, $c", [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; // Extra precision multiplies with low / high results -def SMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), +def SMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), "smull", " $ldst, $hdst, $a, $b", []>; -def UMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), +def UMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), "umull", " $ldst, $hdst, $a, $b", []>; // Multiply + accumulate -def SMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), +def SMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), "smlal", " $ldst, $hdst, $a, $b", []>; -def UMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), +def UMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), "umlal", " $ldst, $hdst, $a, $b", []>; -def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), +def UMAAL : AI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), "umaal", " $ldst, $hdst, $a, $b", []>, Requires<[IsARM, HasV6]>; // Most significant word multiply -def SMMUL : AI<(ops GPR:$dst, GPR:$a, GPR:$b), +def SMMUL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), "smmul", " $dst, $a, $b", [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, Requires<[IsARM, HasV6]>; -def SMMLA : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), +def SMMLA : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), "smmla", " $dst, $a, $b, $c", [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, Requires<[IsARM, HasV6]>; -def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), +def SMMLS : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), "smmls", " $dst, $a, $b, $c", [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, Requires<[IsARM, HasV6]>; multiclass AI_smul<string opc, PatFrag opnode> { - def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), + def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "bb"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), (sext_inreg GPR:$b, i16)))]>, Requires<[IsARM, HasV5TE]>; - def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), + def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "bt"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), (sra GPR:$b, 16)))]>, Requires<[IsARM, HasV5TE]>; - def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), + def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "tb"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sra GPR:$a, 16), (sext_inreg GPR:$b, i16)))]>, Requires<[IsARM, HasV5TE]>; - def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), + def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "tt"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sra GPR:$a, 16), (sra GPR:$b, 16)))]>, Requires<[IsARM, HasV5TE]>; - def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), + def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "wb"), " $dst, $a, $b", [(set GPR:$dst, (sra (opnode GPR:$a, (sext_inreg GPR:$b, i16)), 16))]>, Requires<[IsARM, HasV5TE]>; - def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), + def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "wt"), " $dst, $a, $b", [(set GPR:$dst, (sra (opnode GPR:$a, (sra GPR:$b, 16)), 16))]>, @@ -1050,34 +1074,34 @@ multiclass AI_smul<string opc, PatFrag opnode> { } multiclass AI_smla<string opc, PatFrag opnode> { - def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), + def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "bb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), (sext_inreg GPR:$b, i16))))]>, Requires<[IsARM, HasV5TE]>; - def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), + def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "bt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), (sra GPR:$b, 16))))]>, Requires<[IsARM, HasV5TE]>; - def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), + def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "tb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), (sext_inreg GPR:$b, i16))))]>, Requires<[IsARM, HasV5TE]>; - def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), + def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "tt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), (sra GPR:$b, 16))))]>, Requires<[IsARM, HasV5TE]>; - def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), + def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "wb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, (sext_inreg GPR:$b, i16)), 16)))]>, Requires<[IsARM, HasV5TE]>; - def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), + def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "wt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, (sra GPR:$b, 16)), 16)))]>, @@ -1094,15 +1118,15 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; // Misc. Arithmetic Instructions. // -def CLZ : AI<(ops GPR:$dst, GPR:$src), +def CLZ : AI<(outs GPR:$dst), (ins GPR:$src), "clz", " $dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>; -def REV : AI<(ops GPR:$dst, GPR:$src), +def REV : AI<(outs GPR:$dst), (ins GPR:$src), "rev", " $dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>; -def REV16 : AI<(ops GPR:$dst, GPR:$src), +def REV16 : AI<(outs GPR:$dst), (ins GPR:$src), "rev16", " $dst, $src", [(set GPR:$dst, (or (and (srl GPR:$src, 8), 0xFF), @@ -1111,7 +1135,7 @@ def REV16 : AI<(ops GPR:$dst, GPR:$src), (and (shl GPR:$src, 8), 0xFF000000)))))]>, Requires<[IsARM, HasV6]>; -def REVSH : AI<(ops GPR:$dst, GPR:$src), +def REVSH : AI<(outs GPR:$dst), (ins GPR:$src), "revsh", " $dst, $src", [(set GPR:$dst, (sext_inreg @@ -1119,7 +1143,7 @@ def REVSH : AI<(ops GPR:$dst, GPR:$src), (shl GPR:$src, 8)), i16))]>, Requires<[IsARM, HasV6]>; -def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt), +def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), "pkhbt", " $dst, $src1, $src2, LSL $shamt", [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), (and (shl GPR:$src2, (i32 imm:$shamt)), @@ -1133,7 +1157,7 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; -def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt), +def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), "pkhtb", " $dst, $src1, $src2, ASR $shamt", [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), (and (sra GPR:$src2, imm16_31:$shamt), @@ -1172,17 +1196,17 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), // Conditional moves // FIXME: should be able to write a pattern for ARMcmov, but can't use // a two-value operand where a dag node expects two operands. :( -def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true), +def MOVCCr : AI<(outs GPR:$dst), (ins GPR:$false, GPR:$true), "mov", " $dst, $true", [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $dst">; -def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true), +def MOVCCs : AI<(outs GPR:$dst), (ins GPR:$false, so_reg:$true), "mov", " $dst, $true", [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $dst">; -def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true), +def MOVCCi : AI<(outs GPR:$dst), (ins GPR:$false, so_imm:$true), "mov", " $dst, $true", [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $dst">; @@ -1190,14 +1214,14 @@ def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true), // LEApcrel - Load a pc-relative address into a register without offending the // assembler. -def LEApcrel : AXI1<(ops GPR:$dst, i32imm:$label, pred:$p), +def LEApcrel : AXI1<(outs GPR:$dst), (ins i32imm:$label, pred:$p), !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", "${:private}PCRELL${:uid}+8))\n"), !strconcat("${:private}PCRELL${:uid}:\n\t", "add$p $dst, pc, #PCRELV${:uid}")), []>; -def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p), +def LEApcrelJT : AXI1<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+8))\n"), !strconcat("${:private}PCRELL${:uid}:\n\t", @@ -1211,7 +1235,7 @@ def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p), // __aeabi_read_tp preserves the registers r1-r3. let isCall = 1, Defs = [R0, R12, LR, CPSR] in { - def TPsoft : AXI<(ops), + def TPsoft : AXI<(outs), (ins), "bl __aeabi_read_tp", [(set R0, ARMthread_pointer)]>; } @@ -1230,7 +1254,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), // Two piece so_imms. let isReMaterializable = 1 in -def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src), +def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), "mov", " $dst, $src", [(set GPR:$dst, so_imm2part:$src)]>; diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 27231daf13..757b876b01 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -29,38 +29,39 @@ class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> { list<Predicate> Predicates = [IsThumb, HasV5T]; } -class ThumbI<dag ops, AddrMode am, SizeFlagVal sz, +class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, string asm, string cstr, list<dag> pattern> // FIXME: Set all opcodes to 0 for now. : InstARM<0, am, sz, IndexModeNone, cstr> { - let OperandList = ops; + let OutOperandList = outs; + let InOperandList = ins; let AsmString = asm; let Pattern = pattern; list<Predicate> Predicates = [IsThumb]; } -class TI<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>; -class TI1<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>; -class TI2<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>; -class TI4<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>; -class TIs<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>; +class TI<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>; +class TI1<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>; +class TI2<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>; +class TI4<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>; +class TIs<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>; // Two-address instructions -class TIt<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; +class TIt<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; // BL, BLX(1) are translated by assembler into two instructions -class TIx2<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>; +class TIx2<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; // BR_JT instructions -class TJTI<dag ops, string asm, list<dag> pattern> - : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>; +class TJTI<dag outs, dag ins, string asm, list<dag> pattern> + : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>; def imm_neg_XFORM : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32); @@ -160,17 +161,17 @@ def t_addrmode_sp : Operand<i32>, // def tADJCALLSTACKUP : -PseudoInst<(ops i32imm:$amt), +PseudoInst<(outs), (ins i32imm:$amt), "@ tADJCALLSTACKUP $amt", [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>; def tADJCALLSTACKDOWN : -PseudoInst<(ops i32imm:$amt), +PseudoInst<(outs), (ins i32imm:$amt), "@ tADJCALLSTACKDOWN $amt", [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>; let isNotDuplicable = 1 in -def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp), +def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), "$cp:\n\tadd $dst, pc", [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; @@ -179,120 +180,122 @@ def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp), // let isReturn = 1, isTerminator = 1 in { - def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>; + def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>; // Alternative return instruction used by vararg functions. - def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>; + def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>; } // FIXME: remove when we have a way to marking a MI with these properties. let isLoad = 1, isReturn = 1, isTerminator = 1 in -def tPOP_RET : TI<(ops reglist:$dst1, variable_ops), +def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; let isCall = 1, noResults = 1, Defs = [R0, R1, R2, R3, LR, D0, D1, D2, D3, D4, D5, D6, D7] in { - def tBL : TIx2<(ops i32imm:$func, variable_ops), + def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), "bl ${func:call}", [(ARMtcall tglobaladdr:$func)]>; // ARMv5T and above - def tBLXi : TIx2<(ops i32imm:$func, variable_ops), + def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), "blx ${func:call}", [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>; - def tBLXr : TI<(ops GPR:$dst, variable_ops), - "blx $dst", - [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>; + def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), + "blx $func", + [(ARMtcall GPR:$func)]>, Requires<[HasV5T]>; // ARMv4T - def tBX : TIx2<(ops GPR:$dst, variable_ops), - "cpy lr, pc\n\tbx $dst", - [(ARMcall_nolink GPR:$dst)]>; + def tBX : TIx2<(outs), (ins GPR:$func, variable_ops), + "cpy lr, pc\n\tbx $func", + [(ARMcall_nolink GPR:$func)]>; } let isBranch = 1, isTerminator = 1, noResults = 1 in { let isBarrier = 1 in { let isPredicable = 1 in - def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>; + def tB : TI<(outs), (ins brtarget:$target), "b $target", + [(br bb:$target)]>; // Far jump - def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>; + def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>; - def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id), - "cpy pc, $dst \n\t.align\t2\n$jt", - [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>; + def tBR_JTr : TJTI<(outs), + (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), + "cpy pc, $target \n\t.align\t2\n$jt", + [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; } } // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node expects two operands. :( let isBranch = 1, isTerminator = 1, noResults = 1 in - def tBcc : TI<(ops brtarget:$dst, pred:$cc), "b$cc $dst", - [/*(ARMbrcond bb:$dst, imm:$cc)*/]>; + def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target", + [/*(ARMbrcond bb:$target, imm:$cc)*/]>; //===----------------------------------------------------------------------===// // Load Store Instructions. // let isLoad = 1 in { -def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr), +def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load t_addrmode_s4:$addr))]>; -def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr), +def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr), "ldrb $dst, $addr", [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>; -def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr), +def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr), "ldrh $dst, $addr", [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>; -def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr), +def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr), "ldrsb $dst, $addr", [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; -def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr), +def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr), "ldrsh $dst, $addr", [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; -def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr), +def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load t_addrmode_sp:$addr))]>; // Special instruction for restore. It cannot clobber condition register // when it's expanded by eliminateCallFramePseudoInstr(). -def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr), +def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), "ldr $dst, $addr", []>; // Load tconstpool -def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr), +def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; // Special LDR for loads from non-pc-relative constpools. let isReMaterializable = 1 in -def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr), +def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", []>; } // isLoad let isStore = 1 in { -def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr), +def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr), "str $src, $addr", [(store GPR:$src, t_addrmode_s4:$addr)]>; -def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr), +def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr), "strb $src, $addr", [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>; -def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr), +def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr), "strh $src, $addr", [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>; -def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr), +def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), "str $src, $addr", [(store GPR:$src, t_addrmode_sp:$addr)]>; // Special instruction for spill. It cannot clobber condition register // when it's expanded by eliminateCallFramePseudoInstr(). -def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr), +def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), "str $src, $addr", []>; } @@ -303,11 +306,11 @@ def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr), // TODO: A7-44: LDMIA - load multiple let isLoad = 1 in -def tPOP : TI<(ops reglist:$dst1, variable_ops), +def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; let isStore = 1 in -def tPUSH : TI<(ops reglist:$src1, variable_ops), +def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops), "push $src1", []>; //===----------------------------------------------------------------------===// @@ -315,106 +318,106 @@ def tPUSH : TI<(ops reglist:$src1, variable_ops), // // Add with carry -def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "adc $dst, $rhs", [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>; -def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "add $dst, $lhs, $rhs", [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>; -def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "add $dst, $lhs, $rhs", [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>; -def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "add $dst, $rhs", [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>; -def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "add $dst, $lhs, $rhs", [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>; -def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "add $dst, $rhs", []>; -def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs), +def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs), "add $dst, pc, $rhs * 4", []>; -def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs), +def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs), "add $dst, $sp, $rhs * 4", []>; -def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "add $dst, $rhs * 4", []>; -def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "and $dst, $rhs", [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>; -def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "asr $dst, $lhs, $rhs", [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>; -def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "asr $dst, $rhs", [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>; -def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "bic $dst, $rhs", [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>; -def tCMN : TI<(ops GPR:$lhs, GPR:$rhs), +def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs), "cmn $lhs, $rhs", [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>; -def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs), +def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>; -def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs), +def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs), "cmp $lhs, $rhs", [(ARMcmp GPR:$lhs, GPR:$rhs)]>; -def tTST : TI<(ops GPR:$lhs, GPR:$rhs), +def tTST : TI<(outs), (ins GPR:$lhs, GPR:$rhs), "tst $lhs, $rhs", [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>; -def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs), +def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs), "cmn $lhs, $rhs", [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>; -def tCMPNZi8 : TI<(ops GPR:$lhs, i32imm:$rhs), +def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>; -def tCMPNZr : TI<(ops GPR:$lhs, GPR:$rhs), +def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs), "cmp $lhs, $rhs", [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>; // TODO: A7-37: CMP(3) - cmp hi regs -def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "eor $dst, $rhs", [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>; -def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "lsl $dst, $lhs, $rhs", [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>; -def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "lsl $dst, $rhs", [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>; -def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "lsr $dst, $lhs, $rhs", [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>; -def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "lsr $dst, $rhs", [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>; // FIXME: This is not rematerializable because mov changes the condition code. -def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src), +def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src), "mov $dst, $src", [(set GPR:$dst, imm0_255:$src)]>; @@ -423,32 +426,32 @@ def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src), // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy', // which is MOV(3). This also supports high registers. -def tMOVr : TI<(ops GPR:$dst, GPR:$src), +def tMOVr : TI<(outs GPR:$dst), (ins GPR:$src), "cpy $dst, $src", []>; -def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "mul $dst, $rhs", [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>; -def tMVN : TI<(ops GPR:$dst, GPR:$src), +def tMVN : TI<(outs GPR:$dst), (ins GPR:$src), "mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; -def tNEG : TI<(ops GPR:$dst, GPR:$src), +def tNEG : TI<(outs GPR:$dst), (ins GPR:$src), "neg $dst, $src", [(set GPR:$dst, (ineg GPR:$src))]>; -def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "orr $dst, $rhs", [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>; -def tREV : TI<(ops GPR:$dst, GPR:$src), +def tREV : TI<(outs GPR:$dst), (ins GPR:$src), "rev $dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsThumb, HasV6]>; -def tREV16 : TI<(ops GPR:$dst, GPR:$src), +def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src), "rev16 $dst, $src", [(set GPR:$dst, (or (and (srl GPR:$src, 8), 0xFF), @@ -457,7 +460,7 @@ def tREV16 : TI<(ops GPR:$dst, GPR:$src), (and (shl GPR:$src, 8), 0xFF000000)))))]>, Requires<[IsThumb, HasV6]>; -def tREVSH : TI<(ops GPR:$dst, GPR:$src), +def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src), "revsh $dst, $src", [(set GPR:$dst, (sext_inreg @@ -465,53 +468,53 @@ def tREVSH : TI<(ops GPR:$dst, GPR:$src), (shl GPR:$src, 8)), i16))]>, Requires<[IsThumb, HasV6]>; -def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "ror $dst, $rhs", [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>; // Subtract with carry -def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "sbc $dst, $rhs", [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>; -def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "sub $dst, $lhs, $rhs", [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>; // TODO: A7-96: STMIA - store multiple. -def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "sub $dst, $lhs, $rhs", [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>; -def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "sub $dst, $rhs", [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>; -def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), +def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), "sub $dst, $lhs, $rhs", [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>; -def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), +def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "sub $dst, $rhs * 4", []>; -def tSXTB : TI<(ops GPR:$dst, GPR:$src), +def tSXTB : TI<(outs GPR:$dst), (ins GPR:$src), "sxtb $dst, $src", [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>, Requires<[IsThumb, HasV6]>; -def tSXTH : TI<(ops GPR:$dst, GPR:$src), +def tSXTH : TI<(outs GPR:$dst), (ins GPR:$src), "sxth $dst, $src", [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>, Requires<[IsThumb, HasV6]>; -def tUXTB : TI<(ops GPR:$dst, GPR:$src), +def tUXTB : TI<(outs GPR:$dst), (ins GPR:$src), "uxtb $dst, $src", [(set GPR:$dst, (and GPR:$src, 0xFF))]>, Requires<[IsThumb, HasV6]>; -def tUXTH : TI<(ops GPR:$dst, GPR:$src), +def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src), "uxth $dst, $src", [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>, Requires<[IsThumb, HasV6]>; @@ -521,20 +524,20 @@ def tUXTH : TI<(ops GPR:$dst, GPR:$src), // Expanded by the scheduler into a branch sequence. let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. def tMOVCCr : - PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, pred:$cc), + PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc), "@ tMOVCCr $cc", [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>; // tLEApcrel - Load a pc-relative address into a register without offending the // assembler. -def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label), +def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label), !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", "${:private}PCRELL${:uid}+4))\n"), !strconcat("\tmov $dst, #PCRELV${:uid}\n", "${:private}PCRELL${:uid}:\n\tadd $dst, pc")), []>; -def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id), +def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id), !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+4))\n"), !strconcat("\tmov $dst, #PCRELV${:uid}\n", @@ -548,7 +551,7 @@ def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id), // __aeabi_read_tp preserves the registers r1-r3. let isCall = 1, Defs = [R0, LR] in { - def tTPsoft : TIx2<(ops), + def tTPsoft : TIx2<(outs), (ins), "bl __aeabi_read_tp", [(set R0, ARMthread_pointer)]>; } diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 4bb9f0462e..c89c9640e7 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -16,45 +16,45 @@ // // ARM Float Instruction -class ASI<dag ops, string opc, string asm, list<dag> pattern> - : AI<ops, opc, asm, pattern> { +class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern> + : AI<outs, ins, opc, asm, pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } -class ASI5<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> { +class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern> + : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } // ARM Double Instruction -class ADI<dag ops, string opc, string asm, list<dag> pattern> - : AI<ops, opc, asm, pattern> { +class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern> + : AI<outs, ins, opc, asm, pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } -class ADI5<dag ops, string opc, string asm, list<dag> pattern> - : I<ops, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> { +class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern> + : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } // Special cases. -class AXSI<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> { +class AXSI<dag outs, dag ins, string asm, list<dag> pattern> + : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } -class AXSI5<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> { +class AXSI5<dag outs, dag ins, string asm, list<dag> pattern> + : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } -class AXDI<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> { +class AXDI<dag outs, dag ins, string asm, list<dag> pattern> + : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } -class AXDI5<dag ops, string asm, list<dag> pattern> - : XI<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> { +class AXDI5<dag outs, dag ins, string asm, list<dag> pattern> + : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> { // TODO: Mark the instructions with the appropriate subtarget info. } @@ -83,21 +83,21 @@ def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>; // let isLoad = 1 in { -def FLDD : ADI5<(ops DPR:$dst, addrmode5:$addr), +def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr), "fldd", " $dst, $addr", [(set DPR:$dst, (load addrmode5:$addr))]>; -def FLDS : ASI5<(ops SPR:$dst, addrmode5:$addr), +def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr), "flds", " $dst, $addr", [(set SPR:$dst, (load addrmode5:$addr))]>; } // isLoad let isStore = 1 in { -def FSTD : ADI5<(ops DPR:$src, addrmode5:$addr), +def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr), "fstd", " $src, $addr", [(store DPR:$src, addrmode5:$addr)]>; -def FSTS : ASI5<(ops SPR:$src, addrmode5:$addr), +def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr), "fsts", " $src, $addr", [(store SPR:$src, addrmode5:$addr)]>; } // isStore @@ -107,21 +107,25 @@ def FSTS : ASI5<(ops SPR:$src, addrmode5:$addr), // let isLoad = 1 in { -def FLDMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), +def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, + variable_ops), "fldm${addr:submode}d${p} ${addr:base}, $dst1", []>; -def FLDMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), +def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, + variable_ops), "fldm${addr:submode}s${p} ${addr:base}, $dst1", []>; } // isLoad let isStore = 1 in { -def FSTMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops), +def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, + variable_ops), "fstm${addr:submode}d${p} ${addr:base}, $src1", []>; -def FSTMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops), +def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, + variable_ops), "fstm${addr:submode}s${p} ${addr:base}, $src1", []>; } // isStore @@ -132,43 +136,43 @@ def FSTMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops), // FP Binary Operations. // -def FADDD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b), +def FADDD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b), "faddd", " $dst, $a, $b", [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>; -def FADDS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b), +def FADDS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b), "fadds", " $dst, $a, $b", [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>; -def FCMPED : ADI<(ops DPR:$a, DPR:$b), +def FCMPED : ADI<(outs), (ins DPR:$a, DPR:$b), "fcmped", " $a, $b", [(arm_cmpfp DPR:$a, DPR:$b)]>; -def FCMPES : ASI<(ops SPR:$a, SPR:$b), +def FCMPES : ASI<(outs), (ins SPR:$a, SPR:$b), "fcmpes", " $a, $b", [(arm_cmpfp SPR:$a, SPR:$b)]>; -def FDIVD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b), +def FDIVD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b), "fdivd", " $dst, $a, $b", [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>; -def FDIVS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b), +def FDIVS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b), "fdivs", " $dst, $a, $b", [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>; -def FMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b), +def FMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b), "fmuld", " $dst, $a, $b", [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>; -def FMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b), +def FMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b), "fmuls", " $dst, $a, $b", [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>; -def FNMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b), +def FNMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b), "fnmuld", " $dst, $a, $b", [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>; -def FNMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b), +def FNMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b), "fnmuls", " $dst, $a, $b", [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>; @@ -179,11 +183,11 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b), (FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; -def FSUBD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b), +def FSUBD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b), "fsubd", " $dst, $a, $b", [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>; -def FSUBS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b), +def FSUBS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b), "fsubs", " $dst, $a, $b", [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>; @@ -191,49 +195,49 @@ def FSUBS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b), // FP Unary Operations. // -def FABSD : ADI<(ops DPR:$dst, DPR:$a), +def FABSD : ADI<(outs DPR:$dst), (ins DPR:$a), "fabsd", " $dst, $a", [(set DPR:$dst, (fabs DPR:$a))]>; -def FABSS : ASI<(ops SPR:$dst, SPR:$a), +def FABSS : ASI<(outs SPR:$dst), (ins SPR:$a), "fabss", " $dst, $a", [(set SPR:$dst, (fabs SPR:$a))]>; -def FCMPEZD : ADI<(ops DPR:$a), +def FCMPEZD : ADI<(outs), (ins DPR:$a), "fcmpezd", " $a", [(arm_cmpfp0 DPR:$a)]>; -def FCMPEZS : ASI<(ops SPR:$a), +def FCMPEZS : ASI<(outs), (ins SPR:$a), "fcmpezs", " $a", [(arm_cmpfp0 SPR:$a)]>; -def FCVTDS : ADI<(ops DPR:$dst, SPR:$a), +def FCVTDS : ADI<(outs DPR:$dst), (ins SPR:$a), "fcvtds", " $dst, $a", [(set DPR:$dst, (fextend SPR:$a))]>; -def FCVTSD : ADI<(ops SPR:$dst, DPR:$a), +def FCVTSD : ADI<(outs SPR:$dst), (ins DPR:$a), "fcvtsd", " $dst, $a", [(set SPR:$dst, (fround DPR:$a))]>; -def FCPYD : ADI<(ops DPR:$dst, DPR:$a), +def FCPYD : ADI<(outs DPR:$dst), (ins DPR:$a), "fcpyd", " $dst, $a", []>; -def FCPYS : ASI<(ops SPR:$dst, SPR:$a), +def FCPYS : ASI<(outs SPR:$dst), (ins SPR:$a), "fcpys", " $dst, $a", []>; -def FNEGD : ADI<(ops DPR:$dst, DPR:$a), +def FNEGD : ADI<(outs DPR:$dst), (ins DPR:$a), "fnegd", " $dst, $a", [(set DPR:$dst, (fneg DPR:$a))]>; -def FNEGS : ASI<(ops SPR:$dst, SPR:$a), +def FNEGS : ASI<(outs SPR:$dst), (ins SPR:$a), "fnegs", " $dst, $a", [(set SPR:$dst, (fneg SPR:$a))]>; -def FSQRTD : ADI<(ops DPR:$dst, DPR:$a), +def FSQRTD : ADI<(outs DPR:$dst), (ins DPR:$a), "fsqrtd", " $dst, $a", [(set DPR:$dst, (fsqrt DPR:$a))]>; -def FSQRTS : ASI<(ops SPR:$dst, SPR:$a), +def FSQRTS : ASI<(outs SPR:$dst), (ins SPR:$a), "fsqrts", " $dst, $a", [(set SPR:$dst, (fsqrt SPR:$a))]>; @@ -241,30 +245,30 @@ def FSQRTS : ASI<(ops SPR:$dst, SPR:$a), // FP <-> GPR Copies. Int <-> FP Conversions. // -def IMPLICIT_DEF_SPR : PseudoInst<(ops SPR:$rD, pred:$p), +def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p), "@ IMPLICIT_DEF_SPR $rD", [(set SPR:$rD, (undef))]>; -def IMPLICIT_DEF_DPR : PseudoInst<(ops DPR:$rD, pred:$p), +def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p), "@ IMPLICIT_DEF_DPR $rD", [(set DPR:$rD, (undef))]>; -def FMRS : ASI<(ops GPR:$dst, SPR:$src), +def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src), "fmrs", " $dst, $src", [(set GPR:$dst, (bitconvert SPR:$src))]>; -def FMSR : ASI<(ops SPR:$dst, GPR:$src), +def FMSR : ASI<(outs SPR:$dst), (ins GPR:$src), "fmsr", " $dst, $src", [(set SPR:$dst, (bitconvert GPR:$src))]>; -def FMRRD : ADI<(ops GPR:$dst1, GPR:$dst2, DPR:$src), +def FMRRD : ADI<(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src), "fmrrd", " $dst1, $dst2, $src", [/* FIXME: Can't write pattern for multiple result instr*/]>; // FMDHR: GPR -> SPR // FMDLR: GPR -> SPR -def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2), +def FMDRR : ADI<(outs DPR:$dst), (ins GPR:$src1, GPR:$src2), "fmdrr", " $dst, $src1, $src2", [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>; @@ -275,45 +279,45 @@ def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2), // FMSRR: GPR -> SPR -def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>; +def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>; // FMXR: GPR -> VFP Sstem reg // Int to FP: -def FSITOD : ADI<(ops DPR:$dst, SPR:$a), +def FSITOD : ADI<(outs DPR:$dst), (ins SPR:$a), "fsitod", " $dst, $a", [(set DPR:$dst, (arm_sitof SPR:$a))]>; -def FSITOS : ASI<(ops SPR:$dst, SPR:$a), +def FSITOS : ASI<(outs SPR:$dst), (ins SPR:$a), "fsitos", " $dst, $a", [(set SPR:$dst, (arm_sitof SPR:$a))]>; -def FUITOD : ADI<(ops DPR:$dst, SPR:$a), +def FUITOD : ADI<(outs DPR:$dst), (ins SPR:$a), "fuitod", " $dst, $a", [(set DPR:$dst, (arm_uitof SPR:$a))]>; -def FUITOS : ASI<(ops SPR:$dst, SPR:$a), +def FUITOS : ASI<(outs SPR:$dst), (ins SPR:$a), "fuitos", " $dst, $a", [(set SPR:$dst, (arm_uitof SPR:$a))]>; // FP to Int: // Always set Z bit in the instruction, i.e. "round towards zero" variants. -def FTOSIZD : ADI<(ops SPR:$dst, DPR:$a), +def FTOSIZD : ADI<(outs SPR:$dst), (ins DPR:$a), "ftosizd", " $dst, $a", [(set SPR:$dst, (arm_ftosi DPR:$a))]>; -def FTOSIZS : ASI<(ops SPR:$dst, SPR:$a), +def FTOSIZS : ASI<(outs SPR:$dst), (ins SPR:$a), "ftosizs", " $dst, $a", [(set SPR:$dst, (arm_ftosi SPR:$a))]>; -def FTOUIZD : ADI<(ops SPR:$dst, DPR:$a), +def FTOUIZD : ADI<(outs SPR:$dst), (ins DPR:$a), "ftouizd", " $dst, $a", [(set SPR:$dst, (arm_ftoui DPR:$a))]>; -def FTOUIZS : ASI<(ops SPR:$dst, SPR:$a), +def FTOUIZS : ASI<(outs SPR:$dst), (ins SPR:$a), "ftouizs", " $dst, $a", [(set SPR:$dst, (arm_ftoui SPR:$a))]>; @@ -321,42 +325,42 @@ def FTOUIZS : ASI<(ops SPR:$dst, SPR:$a), // FP FMA Operations. // -def FMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b), +def FMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b), "fmacd", " $dst, $a, $b", [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b), +def FMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b), "fmacs", " $dst, $a, $b", [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b), +def FMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b), "fmscd", " $dst, $a, $b", [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b), +def FMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b), "fmscs", " $dst, $a, $b", [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FNMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b), +def FNMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b), "fnmacd", " $dst, $a, $b", [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FNMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b), +def FNMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b), "fnmacs", " $dst, $a, $b", [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FNMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b), +def FNMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b), "fnmscd", " $dst, $a, $b", [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>, RegConstraint<"$dstin = $dst">; -def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b), +def FNMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b), "fnmscs", " $dst, $a, $b", [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>, RegConstraint<"$dstin = $dst">; @@ -365,22 +369,22 @@ def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b), // FP Conditional moves. // -def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true), +def FCPYDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true), "fcpyd", " $dst, $true", [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; -def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true), +def FCPYScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true), "fcpys", " $dst, $true", [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; -def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true), +def FNEGDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true), "fnegd", " $dst, $true", [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; -def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true), +def FNEGScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true), "fnegs", " $dst, $true", [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>, RegConstraint<"$false = $dst">; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index f9d9342fe5..eda31b0ca9 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -327,8 +327,8 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, return NewMI; } -const unsigned* ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) - const { +const unsigned* +ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { static const unsigned CalleeSavedRegs[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index 3db1d89403..a425bb6f90 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -68,8 +68,8 @@ public: const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; - const TargetRegisterClass* const* getCalleeSavedRegClasses( - const MachineFunction *MF = 0) const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index 259e9afe22..1d430f24d5 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -57,7 +57,8 @@ class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { bits<5> Ra; - let OperandList = (ops GPRC:$RA); + let OutOperandList = (ops GPRC:$RA); + let InOperandList = (ops); let Inst{25-21} = Ra; let Inst{20-16} = 0; let Inst{15-0} = fc; @@ -69,7 +70,8 @@ class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass bits<5> Rb; bits<14> disp; - let OperandList = OL; + let OutOperandList = (ops); + let InOperandList = OL; let Inst{25-21} = Ra; let Inst{20-16} = Rb; @@ -83,7 +85,8 @@ class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> patt bits<5> Rb; bits<14> disp; - let OperandList = OL; + let OutOperandList = (ops); + let InOperandList = OL; let Inst{25-21} = Ra; let Inst{20-16} = Rb; @@ -97,7 +100,8 @@ def target : Operand<OtherVT> {} let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in { class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { - let OperandList = OL; + let OutOperandList = (ops); + let InOperandList = OL; bits<64> Opc; //dummy bits<5> Ra; bits<21> disp; @@ -111,7 +115,8 @@ let isBranch = 1, isTerminator = 1 in class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let OperandList = (ops target:$DISP); + let OutOperandList = (ops); + let InOperandList = (ops target:$DISP); bits<5> Ra; bits<21> disp; @@ -123,7 +128,8 @@ class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass it class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let OperandList = (ops GPRC:$RC, GPRC:$RA, GPRC:$RB); + let OutOperandList = (outs GPRC:$RC); + let InOperandList = (ins GPRC:$RA, GPRC:$RB); bits<5> Rc; bits<5> Ra; @@ -141,7 +147,8 @@ class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Instr class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let OperandList = (ops GPRC:$RC, GPRC:$RB); + let OutOperandList = (outs GPRC:$RC); + let InOperandList = (ins GPRC:$RB); bits<5> Rc; bits<5> Rb; @@ -158,7 +165,8 @@ class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Inst class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let OperandList = (ops GPRC:$RDEST, GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE); + let OutOperandList = (outs GPRC:$RDEST); + let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE); let Constraints = "$RFALSE = $RDEST"; let DisableEncoding = "$RFALSE"; @@ -180,7 +188,8 @@ class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Inst class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let OperandList = (ops GPRC:$RC, GPRC:$RA, u8imm:$L); + let OutOperandList = (outs GPRC:$RC); + let InOperandList = (ins GPRC:$RA, u8imm:$L); bits<5> Rc; bits<5> Ra; @@ -197,7 +206,8 @@ class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Inst class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let OperandList = (ops GPRC:$RDEST, GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE); + let OutOperandList = (outs GPRC:$RDEST); + let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE); let Constraints = "$RFALSE = $RDEST"; let DisableEncoding = "$RFALSE"; @@ -233,7 +243,8 @@ class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, Ins //3.3.5 class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { - let OperandList = OL; + let OutOperandList = (ops); + let InOperandList = OL; bits<26> Function; let Inst{25-0} = Function; @@ -241,9 +252,10 @@ class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> // Pseudo instructions. -class PseudoInstAlpha<dag OL, string nm, list<dag> pattern, InstrItinClass itin> +class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin> : InstAlpha<0, nm, itin> { - let OperandList = OL; + let OutOperandList = OOL; + let InOperandList = IOL; let Pattern = pattern; } diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 4a834da5a8..7470a2f1c0 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -138,24 +138,24 @@ class CmpOpFrag<dag res> : PatFrag<(ops node:$R), res>; //Pseudo ops for selection -def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), ";#idef $RA", +def IDEF_I : PseudoInstAlpha<(outs GPRC:$RA), (ins), ";#idef $RA", [(set GPRC:$RA, (undef))], s_pseudo>; -def IDEF_F32 : PseudoInstAlpha<(ops F4RC:$RA), ";#idef $RA", +def IDEF_F32 : PseudoInstAlpha<(outs F4RC:$RA), (ins), ";#idef $RA", [(set F4RC:$RA, (undef))], s_pseudo>; -def IDEF_F64 : PseudoInstAlpha<(ops F8RC:$RA), ";#idef $RA", +def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA", [(set F8RC:$RA, (undef))], s_pseudo>; -def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", [], s_pseudo>; +def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>; let isLoad = 1, hasCtrlDep = 1 in { -def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt", +def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJUP $amt", [(callseq_start imm:$amt)], s_pseudo>, Imp<[R30],[R30]>; -def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "; ADJDOWN $amt", +def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJDOWN $amt", [(callseq_end imm:$amt)], s_pseudo>, Imp<[R30],[R30]>; } -def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>; -def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>; -def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m), +def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>; +def PCLABEL : PseudoInstAlpha<(outs), (ins s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>; +def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m), "LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>; @@ -404,7 +404,7 @@ let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0, def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP", s_jsr>; //Jump to subroutine return -let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in { +let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)", [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow", @@ -421,8 +421,10 @@ def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)", [(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow", [(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; +} +let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in { def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)", [(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>; def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow", @@ -439,8 +441,10 @@ def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)", [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>; def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow", [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>; +} //Load address +let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)", [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>; def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow", @@ -451,21 +455,25 @@ def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh", [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address high } -let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in { +let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in { def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)", [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>; def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow", [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>; +} +let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)", [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>; def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow", [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>; } -let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in { +let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in { def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)", [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>; def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow", [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>; +} +let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)", [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>; def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow", @@ -541,13 +549,13 @@ def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr), //load address, rellocated gpdist form -let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in { +let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in { def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address } //Load quad, rellocated literal form -let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in +let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal", [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>; def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB), @@ -560,11 +568,11 @@ def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA", s_rpcc>; //Read process cycle count //Floats -let OperandList = (ops F4RC:$RC, F4RC:$RB), Fa = 31 in +let OutOperandList = (ops F4RC:$RC), InOperandList = (ops F4RC:$RB), Fa = 31 in def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RB,$RC", [(set F4RC:$RC, (fsqrt F4RC:$RB))], s_fsqrts>; -let OperandList = (ops F4RC:$RC, F4RC:$RA, F4RC:$RB) in { +let OutOperandList = (ops F4RC:$RC), InOperandList = (ops F4RC:$RA, F4RC:$RB) in { def ADDS : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC", [(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))], s_fadd>; def SUBS : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC", @@ -583,11 +591,11 @@ def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC", //Doubles -let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops F8RC:$RB), Fa = 31 in def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RB,$RC", [(set F8RC:$RC, (fsqrt F8RC:$RB))], s_fsqrtt>; -let OperandList = (ops F8RC:$RC, F8RC:$RA, F8RC:$RB) in { +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops F8RC:$RA, F8RC:$RB) in { def ADDT : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC", [(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))], s_fadd>; def SUBT : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC", @@ -614,13 +622,13 @@ def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", [], s_fadd>; } //More CPYS forms: -let OperandList = (ops F8RC:$RC, F4RC:$RA, F8RC:$RB) in { +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops F4RC:$RA, F8RC:$RB) in { def CPYSTs : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC", [(set F8RC:$RC, (fcopysign F8RC:$RB, F4RC:$RA))], s_fadd>; def CPYSNTs : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC", [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F4RC:$RA)))], s_fadd>; } -let OperandList = (ops F4RC:$RC, F8RC:$RA, F4RC:$RB) in { +let OutOperandList = (ops F4RC:$RC), InOperandList = (ops F8RC:$RA, F4RC:$RB) in { def CPYSSt : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC", [(set F4RC:$RC, (fcopysign F4RC:$RB, F8RC:$RA))], s_fadd>; def CPYSESt : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent @@ -629,7 +637,7 @@ def CPYSNSt : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC", } //conditional moves, floats -let OperandList = (ops F4RC:$RDEST, F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND), +let OutOperandList = (ops F4RC:$RDEST), InOperandList = (ops F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND), isTwoAddress = 1 in { def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if = zero def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if >= zero @@ -639,7 +647,7 @@ def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST",[], s_fcmov>; def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if != zero } //conditional moves, doubles -let OperandList = (ops F8RC:$RDEST, F8RC:$RFALSE, F8RC:$RTRUE, F8RC:$RCOND), +let OutOperandList = (ops F8RC:$RDEST), InOperandList = (ops F8RC:$RFALSE, F8RC:$RTRUE, F8RC:$RCOND), isTwoAddress = 1 in { def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST", [], s_fcmov>; def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST", [], s_fcmov>; @@ -739,31 +747,31 @@ def : Pat<(select (setule F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf), -let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in +let OutOperandList = (ops GPRC:$RC), InOperandList = (ops F4RC:$RA), Fb = 31 in def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[], s_ftoi>; //Floating to integer move, S_floating -let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in +let OutOperandList = (ops GPRC:$RC), InOperandList = (ops F8RC:$RA), Fb = 31 in def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC", [(set GPRC:$RC, (bitconvert F8RC:$RA))], s_ftoi>; //Floating to integer move -let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in +let OutOperandList = (ops F4RC:$RC), InOperandList = (ops GPRC:$RA), Fb = 31 in def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[], s_itof>; //Integer to floating move, S_floating -let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops GPRC:$RA), Fb = 31 in def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC", [(set F8RC:$RC, (bitconvert GPRC:$RA))], s_itof>; //Integer to floating move -let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in +let OutOperandList = (ops F4RC:$RC), InOperandList = (ops F8RC:$RB), Fa = 31 in def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC", [(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))], s_fadd>; -let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops F8RC:$RB), Fa = 31 in def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC", [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))], s_fadd>; -let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops F8RC:$RB), Fa = 31 in def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC", [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))], s_fadd>; -let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in +let OutOperandList = (ops F8RC:$RC), InOperandList = (ops F4RC:$RB), Fa = 31 in def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC", [(set F8RC:$RC, (fextend F4RC:$RB))], s_fadd>; -let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in +let OutOperandList = (ops F4RC:$RC), InOperandList = (ops F8RC:$RB), Fa = 31 in def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC", [(set F4RC:$RC, (fround F8RC:$RB))], s_fadd>; diff --git a/lib/Target/IA64/IA64InstrFormats.td b/lib/Target/IA64/IA64InstrFormats.td index ba6c574cd4..f16109ba8c 100644 --- a/lib/Target/IA64/IA64InstrFormats.td +++ b/lib/Target/IA64/IA64InstrFormats.td @@ -16,11 +16,12 @@ // Instruction format superclass //===----------------------------------------------------------------------===// -class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction { +class InstIA64<bits<4> op, dag OOL, dag IOL, string asmstr> : Instruction { // IA64 instruction baseline field bits<41> Inst; let Namespace = "IA64"; - let OperandList = OL; + let OutOperandList = OOL; + let InOperandList = IOL; let AsmString = asmstr; let Inst{40-37} = op; @@ -30,30 +31,30 @@ class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction { //We should have: // A, I, M, F, B, L+X -class AForm<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr> : - InstIA64<opcode, OL, asmstr> { +class AForm<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr> : + InstIA64<opcode, OOL, IOL, asmstr> { let Inst{5-0} = qpReg; } -class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr, +class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr, list<dag> pattern> : - InstIA64<opcode, OL, asmstr> { + InstIA64<opcode, OOL, IOL, asmstr> { let Pattern = pattern; let Inst{5-0} = qpReg; } let isBranch = 1, isTerminator = 1 in -class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OL, string asmstr> : - InstIA64<opcode, OL, asmstr> { +class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OOL, dag IOL, string asmstr> : + InstIA64<opcode, OOL, IOL, asmstr> { let Inst{32-27} = x6; let Inst{8-6} = btype; } -class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> : - InstIA64<opcode, OL, asmstr> { +class MForm<bits<4> opcode, bits<6> x6, dag OOL, dag IOL, string asmstr> : + InstIA64<opcode, OOL, IOL, asmstr> { bits<7> Ra; bits<7> Rb; bits<16> disp; @@ -63,17 +64,17 @@ class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> : let Inst{15-0} = disp; } -class RawForm<bits<4> opcode, bits<26> rest, dag OL, string asmstr> : - InstIA64<opcode, OL, asmstr> { +class RawForm<bits<4> opcode, bits<26> rest, dag OOL, dag IOL, string asmstr> : + InstIA64<opcode, OOL, IOL, asmstr> { let Inst{25-0} = rest; } // Pseudo instructions. -class PseudoInstIA64<dag OL, string nm> : InstIA64<0, OL, nm> { +class PseudoInstIA64<dag OOL, dag IOL, string nm> : InstIA64<0, OOL, IOL, nm> { } -class PseudoInstIA64_DAG<dag OL, string nm, list<dag> pattern> - : InstIA64<0, OL, nm> { +class PseudoInstIA64_DAG<dag OOL, dag IOL, string nm, list<dag> pattern> + : InstIA64<0, OOL, IOL, nm> { let Pattern = pattern; } diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td index 57f5f66851..536e617ef1 100644 --- a/lib/Target/IA64/IA64InstrInfo.td +++ b/lib/Target/IA64/IA64InstrInfo.td @@ -113,49 +113,49 @@ def immSExt14 : PatLeaf<(i64 imm), [{ // field - i.e., true. used to keep movl happy def imm64 : PatLeaf<(i64 imm)>; -def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def ADD : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "add $dst = $src1, $src2", [(set GR:$dst, (add GR:$src1, GR:$src2))]>, isA; -def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def ADD1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "add $dst = $src1, $src2, 1", [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>, isA; -def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm), +def ADDS : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm), "adds $dst = $imm, $src1", [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>, isA; -def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm), +def MOVL : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm), "movl $dst = $imm", [(set GR:$dst, imm64:$imm)]>, isLX; -def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm), +def ADDL_GA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, globaladdress:$imm), "addl $dst = $imm, $src1", []>, isA; // hmm -def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm), +def ADDL_EA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, calltarget:$imm), "addl $dst = $imm, $src1", []>, isA; -def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def SUB : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "sub $dst = $src1, $src2", [(set GR:$dst, (sub GR:$src1, GR:$src2))]>, isA; -def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def SUB1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "sub $dst = $src1, $src2, 1", [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>, isA; let isTwoAddress = 1 in { def TPCADDIMM22 : AForm<0x03, 0x0b, - (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), + (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR:$qp), "($qp) add $dst = $imm, $dst">, isA; def TPCADDS : AForm_DAG<0x03, 0x0b, - (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp), + (outs GR:$dst), (ins GR:$src1, s14imm:$imm, PR:$qp), "($qp) adds $dst = $imm, $dst", []>, isA; def TPCMPIMM8NE : AForm<0x03, 0x0b, - (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp), + (outs PR:$dst), (ins PR:$src1, s22imm:$imm, GR:$src2, PR:$qp), "($qp) cmp.ne $dst , p0 = $imm, $src2">, isA; } @@ -166,65 +166,65 @@ def AXTb : Pat<(anyext PR:$src), (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>; // normal sign/zero-extends -def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src", +def SXT1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt1 $dst = $src", [(set GR:$dst, (sext_inreg GR:$src, i8))]>, isI; -def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src", +def ZXT1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt1 $dst = $src", [(set GR:$dst, (and GR:$src, 255))]>, isI; -def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src", +def SXT2 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt2 $dst = $src", [(set GR:$dst, (sext_inreg GR:$src, i16))]>, isI; -def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src", +def ZXT2 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt2 $dst = $src", [(set GR:$dst, (and GR:$src, 65535))]>, isI; -def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src", +def SXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt4 $dst = $src", [(set GR:$dst, (sext_inreg GR:$src, i32))]>, isI; -def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src", +def ZXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt4 $dst = $src", [(set GR:$dst, (and GR:$src, is32ones))]>, isI; // fixme: shrs vs shru? -def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def MIX1L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "mix1.l $dst = $src1, $src2", [(set GR:$dst, (or (and GR:$src1, isMIX1Lable), (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>, isI; -def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def MIX2L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "mix2.l $dst = $src1, $src2", [(set GR:$dst, (or (and GR:$src1, isMIX2Lable), (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>, isI; -def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def MIX4L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "mix4.l $dst = $src1, $src2", [(set GR:$dst, (or (and GR:$src1, isMIX4Lable), (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>, isI; -def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def MIX1R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "mix1.r $dst = $src1, $src2", [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable), (and GR:$src2, isMIX1Rable)))]>, isI; -def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def MIX2R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "mix2.r $dst = $src1, $src2", [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable), (and GR:$src2, isMIX2Rable)))]>, isI; -def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def MIX4R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "mix4.r $dst = $src1, $src2", [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable), (and GR:$src2, isMIX4Rable)))]>, isI; -def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src), +def GETFSIGD : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins FP:$src), "getf.sig $dst = $src", []>, isM; -def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src), +def SETFSIGD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins GR:$src), "setf.sig $dst = $src", []>, isM; -def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def XMALD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "xma.l $dst = $src1, $src2, $src3", []>, isF; -def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def XMAHD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "xma.h $dst = $src1, $src2, $src3", []>, isF; -def XMAHUD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def XMAHUD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "xma.hu $dst = $src1, $src2, $src3", []>, isF; @@ -239,98 +239,98 @@ def : Pat<(mulhu GR:$src1, GR:$src2), // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add) // has imm form, too -// def ADDS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm), +// def ADDS : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm), // "adds $dst = $imm, $src1">; -def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def AND : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "and $dst = $src1, $src2", [(set GR:$dst, (and GR:$src1, GR:$src2))]>, isA; -def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def ANDCM : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "andcm $dst = $src1, $src2", [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>, isA; // TODO: and/andcm/or/xor/add/sub/shift immediate forms -def OR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def OR : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "or $dst = $src1, $src2", [(set GR:$dst, (or GR:$src1, GR:$src2))]>, isA; -def pOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp), +def pOR : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2, PR:$qp), "($qp) or $dst = $src1, $src2">, isA; // the following are all a bit unfortunate: we throw away the complement // of the compare! -def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.eq $dst, p0 = $src1, $src2", [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>, isA; -def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.gt $dst, p0 = $src1, $src2", [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>, isA; -def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.ge $dst, p0 = $src1, $src2", [(set PR:$dst, (setge GR:$src1, GR:$src2))]>, isA; -def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.lt $dst, p0 = $src1, $src2", [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>, isA; -def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.le $dst, p0 = $src1, $src2", [(set PR:$dst, (setle GR:$src1, GR:$src2))]>, isA; -def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.ne $dst, p0 = $src1, $src2", [(set PR:$dst, (setne GR:$src1, GR:$src2))]>, isA; -def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.ltu $dst, p0 = $src1, $src2", [(set PR:$dst, (setult GR:$src1, GR:$src2))]>, isA; -def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.gtu $dst, p0 = $src1, $src2", [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>, isA; -def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.leu $dst, p0 = $src1, $src2", [(set PR:$dst, (setule GR:$src1, GR:$src2))]>, isA; -def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), +def CMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2), "cmp.geu $dst, p0 = $src1, $src2", [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>, isA; // and we do the whole thing again for FP compares! -def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.eq $dst, p0 = $src1, $src2", [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>, isF; -def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.gt $dst, p0 = $src1, $src2", [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>, isF; -def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.ge $dst, p0 = $src1, $src2", [(set PR:$dst, (setge FP:$src1, FP:$src2))]>, isF; -def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.lt $dst, p0 = $src1, $src2", [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>, isF; -def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.le $dst, p0 = $src1, $src2", [(set PR:$dst, (setle FP:$src1, FP:$src2))]>, isF; -def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.neq $dst, p0 = $src1, $src2", [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF; -def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.lt $dst, p0 = $src1, $src2", [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF; -def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.gt $dst, p0 = $src1, $src2", [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF; -def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.le $dst, p0 = $src1, $src2", [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF; -def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), +def FCMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2), "fcmp.ge $dst, p0 = $src1, $src2", [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF; -def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp), +def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$qp), "($qp) cmp.eq.unc $dst, p0 = r0, r0">, isA; def : Pat<(trunc GR:$src), // truncate i64 to i1 (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true let isTwoAddress=1 in { - def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp), + def TPCMPEQR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp), "($qp) cmp.eq $dst, p0 = r0, r0">, isA; - def TPCMPNER0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp), + def TPCMPNER0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp), "($qp) cmp.ne $dst, p0 = r0, r0">, isA; } @@ -394,47 +394,47 @@ def bXOR : Pat<(xor PR:$src1, PR:$src2), (TPCADDS (ADDS r0, 0), 1, PR:$src2), PR:$src1)>; -def XOR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def XOR : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "xor $dst = $src1, $src2", [(set GR:$dst, (xor GR:$src1, GR:$src2))]>, isA; -def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2), +def SHLADD: AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1,s64imm:$imm,GR:$src2), "shladd $dst = $src1, $imm, $src2", [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>, isA; -def SHL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def SHL : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "shl $dst = $src1, $src2", [(set GR:$dst, (shl GR:$src1, GR:$src2))]>, isI; -def SHRU : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def SHRU : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "shr.u $dst = $src1, $src2", [(set GR:$dst, (srl GR:$src1, GR:$src2))]>, isI; -def SHRS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), +def SHRS : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2), "shr $dst = $src1, $src2", [(set GR:$dst, (sra GR:$src1, GR:$src2))]>, isI; -def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src">, isA; -def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def MOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "mov $dst = $src">, isA; +def FMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "mov $dst = $src">, isF; // XXX: there _is_ no fmov -def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp), +def PMOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src, PR:$qp), "($qp) mov $dst = $src">, isA; -def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst), +def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (outs GR:$dst), (ins), "mov $dst = pr">, isI; -def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src), +def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (outs), (ins GR:$src), "mov pr = $src">, isI; let isTwoAddress = 1 in { - def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp), + def CMOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src2, GR:$src, PR:$qp), "($qp) mov $dst = $src">, isA; } -def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp), +def PFMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src, PR:$qp), "($qp) mov $dst = $src">, isF; let isTwoAddress = 1 in { - def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp), + def CFMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src2, FP:$src, PR:$qp), "($qp) mov $dst = $src">, isF; } @@ -457,223 +457,223 @@ def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using* // TODO: support postincrement (reg, imm9) loads+stores - this needs more // tablegen support -def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">; +def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">; -def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF", +def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF", [(set GR:$reg, (undef))]>; -def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF", +def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF", [(set FP:$reg, (undef))]>; -def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF", +def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF", [(set PR:$reg, (undef))]>; -def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">; -def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops), +def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">; +def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops), "// ADJUSTCALLSTACKUP">; -def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops), +def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(outs), (ins variable_ops), "// ADJUSTCALLSTACKDOWN">; -def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">; +def PSEUDO_ALLOC : PseudoInstIA64<(outs), (ins GR:$foo), "// PSEUDO_ALLOC">; def ALLOC : AForm<0x03, 0x0b, - (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating), + (outs GR:$dst), (ins i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating), "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating">, isM; let isTwoAddress = 1 in { def TCMPNE : AForm<0x03, 0x0b, - (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4), + (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4), "cmp.ne $dst, p0 = $src3, $src4">, isA; def TPCMPEQOR : AForm<0x03, 0x0b, - (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp), + (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp), "($qp) cmp.eq.or $dst, p0 = $src3, $src4">, isA; def TPCMPNE : AForm<0x03, 0x0b, - (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp), + (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp), "($qp) cmp.ne $dst, p0 = $src3, $src4">, isA; def TPCMPEQ : AForm<0x03, 0x0b, - (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp), + (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp), "($qp) cmp.eq $dst, p0 = $src3, $src4">, isA; } -def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm), +def MOVSIMM14 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s14imm:$imm), "mov $dst = $imm">, isA; -def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm), +def MOVSIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s22imm:$imm), "mov $dst = $imm">, isA; -def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm), +def MOVLIMM64 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm), "movl $dst = $imm">, isLX; -def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), +def SHLI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm), "shl $dst = $src1, $imm">, isI; -def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), +def SHRUI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm), "shr.u $dst = $src1, $imm">, isI; -def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), +def SHRSI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm), "shr $dst = $src1, $imm">, isI; def EXTRU : AForm<0x03, 0x0b, - (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), + (outs GR:$dst), (ins GR:$src1, u6imm:$imm1, u6imm:$imm2), "extr.u $dst = $src1, $imm1, $imm2">, isI; def DEPZ : AForm<0x03, 0x0b, - (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), + (outs GR:$dst), (ins GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2">, isI; -def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp), +def PCMPEQOR : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp), "($qp) cmp.eq.or $dst, p0 = $src1, $src2">, isA; -def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp), +def PCMPEQUNC : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp), "($qp) cmp.eq.unc $dst, p0 = $src1, $src2">, isA; -def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp), +def PCMPNE : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp), "($qp) cmp.ne $dst, p0 = $src1, $src2">, isA; // two destinations! -def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2), +def BCMPEQ : AForm<0x03, 0x0b, (outs PR:$dst1, PR:$dst2), (ins GR:$src1, GR:$src2), "cmp.eq $dst1, dst2 = $src1, $src2">, isA; -def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm), +def ADDIMM14 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm), "adds $dst = $imm, $src1">, isA; -def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm), +def ADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm), "add $dst = $imm, $src1">, isA; -def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), +def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR:$qp), "($qp) add $dst = $imm, $src1">, isA; -def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2), +def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2), "sub $dst = $imm, $src2">, isA; let isStore = 1, noResults = 1 in { - def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value), + def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value), "st1 [$dstPtr] = $value">, isM; - def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value), + def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value), "st2 [$dstPtr] = $value">, isM; - def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value), + def ST4 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value), "st4 [$dstPtr] = $value">, isM; - def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value), + def ST8 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value), "st8 [$dstPtr] = $value">, isM; - def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value), + def STF4 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value), "stfs [$dstPtr] = $value">, isM; - def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value), + def STF8 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value), "stfd [$dstPtr] = $value">, isM; - def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value), + def STF_SPILL : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value), "stf.spill [$dstPtr] = $value">, isM; } let isLoad = 1 in { - def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr), + def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), "ld1 $dst = [$srcPtr]">, isM; - def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr), + def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), "ld2 $dst = [$srcPtr]">, isM; - def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr), + def LD4 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), "ld4 $dst = [$srcPtr]">, isM; - def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr), + def LD8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), "ld8 $dst = [$srcPtr]">, isM; - def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr), + def LDF4 : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr), "ldfs $dst = [$srcPtr]">, isM; - def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr), + def LDF8 : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr), "ldfd $dst = [$srcPtr]">, isM; - def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr), + def LDF_FILL : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr), "ldf.fill $dst = [$srcPtr]">, isM; } -def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), +def POPCNT : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "popcnt $dst = $src", [(set GR:$dst, (ctpop GR:$src))]>, isI; // some FP stuff: // TODO: single-precision stuff? -def FADD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2), +def FADD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2), "fadd $dst = $src1, $src2", [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>, isF; -def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2), +def FADDS: AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2), "fadd.s $dst = $src1, $src2">, isF; -def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2), +def FSUB : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2), "fsub $dst = $src1, $src2", [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>, isF; -def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2), +def FMPY : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2), "fmpy $dst = $src1, $src2", [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>, isF; -def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def FMA : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "fma $dst = $src1, $src2, $src3", [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF; -def FMS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def FMS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "fms $dst = $src1, $src2, $src3", [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF; -def FNMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def FNMA : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "fnma $dst = $src1, $src2, $src3", [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>, isF; -def FABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FABS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fabs $dst = $src", [(set FP:$dst, (fabs FP:$src))]>, isF; -def FNEG : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FNEG : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fneg $dst = $src", [(set FP:$dst, (fneg FP:$src))]>, isF; -def FNEGABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FNEGABS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fnegabs $dst = $src", [(set FP:$dst, (fneg (fabs FP:$src)))]>, isF; let isTwoAddress=1 in { def TCFMAS1 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF; def TCFMADS0 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF; } def CFMAS1 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF; def CFNMAS1 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fnma.s1 $dst = $src1, $src2, $src3">, isF; def CFMADS1 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fma.d.s1 $dst = $src1, $src2, $src3">, isF; def CFMADS0 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF; def CFNMADS1 : AForm<0x03, 0x0b, - (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp), + (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp), "($qp) fnma.d.s1 $dst = $src1, $src2, $src3">, isF; -def FRCPAS0 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2), +def FRCPAS0 : AForm<0x03, 0x0b, (outs FP:$dstFR, PR:$dstPR), (ins FP:$src1, FP:$src2), "frcpa.s0 $dstFR, $dstPR = $src1, $src2">, isF; -def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2), +def FRCPAS1 : AForm<0x03, 0x0b, (outs FP:$dstFR, PR:$dstPR), (ins FP:$src1, FP:$src2), "frcpa.s1 $dstFR, $dstPR = $src1, $src2">, isF; -def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), +def XMAL : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3), "xma.l $dst = $src1, $src2, $src3">, isF; -def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTXF : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.xf $dst = $src">, isF; -def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTXUF : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.xuf $dst = $src">, isF; -def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTXUFS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.xuf.s1 $dst = $src">, isF; -def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTFX : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.fx $dst = $src">, isF; -def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTFXU : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.fxu $dst = $src">, isF; -def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTFXTRUNC : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.fx.trunc $dst = $src">, isF; -def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTFXUTRUNC : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.fxu.trunc $dst = $src">, isF; -def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.fx.trunc.s1 $dst = $src">, isF; -def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fcvt.fxu.trunc.s1 $dst = $src">, isF; -def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), +def FNORMD : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src), "fnorm.d $dst = $src">, isF; -def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src), +def GETFD : AForm<0x03, 0x0b, (outs GR:$dst), (ins FP:$src), "getf.d $dst = $src">, isM; -def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src), +def SETFD : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$src), "setf.d $dst = $src">, isM; -def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src), +def GETFSIG : AForm<0x03, 0x0b, (outs GR:$dst), (ins FP:$src), "getf.sig $dst = $src">, isM; -def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src), +def SETFSIG : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$src), "setf.sig $dst = $src">, isM; // these four FP<->int conversion patterns need checking/cleaning @@ -688,11 +688,11 @@ def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)), let isTerminator = 1, isBranch = 1, noResults = 1 in { - def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst), + def BRL_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins i64imm:$dst), "(p0) brl.cond.sptk $dst">, isB; - def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst), + def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst), "($qp) brl.cond.sptk $dst">, isB; - def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst), + def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, GR:$dst), "($qp) br.cond.sptk $dst">, isB; } @@ -713,32 +713,32 @@ let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */ F120,F121,F122,F123,F124,F125,F126,F127, out0,out1,out2,out3,out4,out5,out6,out7] in { // old pattern call - def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst), + def BRCALL: RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst), "br.call.sptk rp = $dst">, isB; // FIXME: teach llvm about branch regs? // new daggy stuff! // calls a globaladdress - def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst), + def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst), "br.call.sptk rp = $dst">, isB; // FIXME: teach llvm about branch regs? // calls an externalsymbol - def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst), + def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst), "br.call.sptk rp = $dst">, isB; // FIXME: teach llvm about branch regs? // calls through a function descriptor - def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg), + def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (outs), (ins GR:$branchreg), "br.call.sptk rp = $branchreg">, isB; // FIXME: teach llvm about branch regs? - def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst), + def BRLCOND_CALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst), "($qp) brl.cond.call.sptk $dst">, isB; - def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst), + def BRCOND_CALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, GR:$dst), "($qp) br.cond.call.sptk $dst">, isB; } // Return branch: let isTerminator = 1, isReturn = 1, noResults = 1 in - def RET : AForm_DAG<0x03, 0x0b, (ops), + def RET : AForm_DAG<0x03, 0x0b, (outs), (ins), "br.ret.sptk.many rp", [(retflag)]>, isB; // return def : Pat<(ret), (RET)>; // the evil stop bit of despair -def STOP : PseudoInstIA64<(ops variable_ops), ";;">; +def STOP : PseudoInstIA64<(outs), (ins variable_ops), ";;">; diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index b88fa90a25..bda63629f3 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -22,7 +22,7 @@ //===----------------------------------------------------------------------===// // Generic Mips Format -class MipsInst<dag ops, string asmstr, list<dag> pattern>: +class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern>: Instruction { field bits<32> Inst; @@ -34,7 +34,8 @@ class MipsInst<dag ops, string asmstr, list<dag> pattern>: // Top 5 bits are the 'opcode' field let Inst{31-26} = opcode; - dag OperandList = ops; + dag OutOperandList = outs; + dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; } @@ -44,8 +45,9 @@ class MipsInst<dag ops, string asmstr, list<dag> pattern>: // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> //===----------------------------------------------------------------------===// -class FR<bits<6> op, bits<6> _funct, dag ops, string asmstr, list<dag> pattern>: - MipsInst<ops, asmstr, pattern> +class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, + list<dag> pattern>: + MipsInst<outs, ins, asmstr, pattern> { bits<5> rd; bits<5> rs; @@ -67,8 +69,8 @@ class FR<bits<6> op, bits<6> _funct, dag ops, string asmstr, list<dag> pattern>: // Format I instruction class in Mips : <|opcode|rs|rt|immediate|> //===----------------------------------------------------------------------===// -class FI<bits<6> op, dag ops, string asmstr, list<dag> pattern>: - MipsInst<ops, asmstr, pattern> +class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: + MipsInst<outs, ins, asmstr, pattern> { bits<5> rt; bits<5> rs; @@ -85,8 +87,8 @@ class FI<bits<6> op, dag ops, string asmstr, list<dag> pattern>: // Format J instruction class in Mips : <|opcode|address|> //===----------------------------------------------------------------------===// -class FJ<bits<6> op, dag ops, string asmstr, list<dag> pattern>: - MipsInst<ops, asmstr, pattern> +class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: + MipsInst<outs, ins, asmstr, pattern> { bits<26> addr; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1f5d152261..9a5ca93f7a 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -106,7 +106,8 @@ let isCommutable = 1 in class ArithR< bits<6> op, bits<6> func, string instr_asm, SDNode OpNode>: FR< op, func, - (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >; @@ -114,7 +115,8 @@ let isCommutable = 1 in class ArithOverflowR< bits<6> op, bits<6> func, string instr_asm>: FR< op, func, - (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, " $dst, $b, $c"), []>; @@ -123,7 +125,8 @@ let isCommutable = 1 in class ArithI<bits<6> op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : FI< op, - (ops CPURegs:$dst, CPURegs:$b, Od:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, Od:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))] >; @@ -132,7 +135,8 @@ let rd=0 in class MArithR<bits<6> func, string instr_asm> : FR< 0x1c, func, - (ops CPURegs:$rs, CPURegs:$rt), + (outs CPURegs:$rs), + (ins CPURegs:$rt), !strconcat(instr_asm, " $rs, $rt"), []>; @@ -140,20 +144,23 @@ class MArithR<bits<6> func, string instr_asm> : class LogicR<bits<6> func, string instr_asm, SDNode OpNode>: FR< 0x00, func, - (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >; class LogicI<bits<6> op, string instr_asm, SDNode OpNode>: FI< op, - (ops CPURegs:$dst, CPURegs:$b, uimm16:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, uimm16:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))]>; class LogicNOR<bits<6> op, bits<6> func, string instr_asm>: FR< op, func, - (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))] >; @@ -162,21 +169,24 @@ let rt = 0 in class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>: FR< 0x00, func, - (ops CPURegs:$dst, CPURegs:$b, shamt:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, shamt:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))] >; class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>: FR< 0x00, func, - (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >; // Load Upper Imediate class LoadUpper<bits<6> op, string instr_asm>: FI< op, - (ops CPURegs:$dst, uimm16:$imm), + (outs CPURegs:$dst), + (ins uimm16:$imm), !strconcat(instr_asm, " $dst, $imm"), []>; @@ -184,14 +194,16 @@ class LoadUpper<bits<6> op, string instr_asm>: let isLoad = 1 in class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>: FI< op, - (ops CPURegs:$dst, mem:$addr), + (outs CPURegs:$dst), + (ins mem:$addr), !strconcat(instr_asm, " $dst, $addr"), [(set CPURegs:$dst, (OpNode addr:$addr))]>; let isStore = 1 in class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>: FI< op, - (ops CPURegs:$dst, mem:$addr), + (outs), + (ins CPURegs:$dst, mem:$addr), !strconcat(instr_asm, " $dst, $addr"), [(OpNode CPURegs:$dst, addr:$addr)]>; @@ -199,7 +211,8 @@ class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>: let isBranch = 1, noResults=1, isTerminator=1 in class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>: FI< op, - (ops CPURegs:$a, CPURegs:$b, brtarget:$offset), + (outs), + (ins CPURegs:$a, CPURegs:$b, brtarget:$offset), !strconcat(instr_asm, " $a, $b, $offset"), [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)]>; @@ -207,14 +220,16 @@ class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op>: FR< op, func, - (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))]>; class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, PatLeaf imm_type>: FI< op, - (ops CPURegs:$dst, CPURegs:$b, Od:$c), + (outs CPURegs:$dst), + (ins CPURegs:$b, Od:$c), !strconcat(instr_asm, " $dst, $b, $c"), [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))]>; @@ -222,7 +237,8 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, let hasCtrlDep=1, noResults=1, isTerminator=1 in class JumpFJ<bits<6> op, string instr_asm>: FJ< op, - (ops brtarget:$target), + (outs), + (ins brtarget:$target), !strconcat(instr_asm, " $target"), [(br bb:$target)]>; @@ -230,7 +246,8 @@ let hasCtrlDep=1, noResults=1, isTerminator=1, rd=0 in class JumpFR<bits<6> op, bits<6> func, string instr_asm>: FR< op, func, - (ops CPURegs:$target), + (outs), + (ins CPURegs:$target), !strconcat(instr_asm, " $target"), []>; @@ -238,7 +255,8 @@ class JumpFR<bits<6> op, bits<6> func, string instr_asm>: let isCall=1 in class JumpLink<bits<6> op, string instr_asm>: FJ< op, - (ops calltarget:$target), + (outs), + (ins calltarget:$target), !strconcat(instr_asm, " $target"), [(MipsJmpLink imm:$target)]>; @@ -246,7 +264,8 @@ let isCall=1 in class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>: FR< op, func, - (ops CPURegs:$rd, CPURegs:$rs), + (outs), + (ins CPURegs:$rd, CPURegs:$rs), !strconcat(instr_asm, " $rs, $rd"), []>; @@ -254,7 +273,8 @@ class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>: class MulDiv<bits<6> func, string instr_asm>: FR< 0x00, func, - (ops CPURegs:$a, CPURegs:$b), + (outs), + (ins CPURegs:$a, CPURegs:$b), !strconcat(instr_asm, " $a, $b"), []>; @@ -262,7 +282,8 @@ class MulDiv<bits<6> func, string instr_asm>: class MoveFromTo<bits<6> func, string instr_asm>: FR< 0x00, func, - (ops CPURegs:$dst), + (outs CPURegs:$dst), + (ins), !strconcat(instr_asm, " $dst"), []>; @@ -270,7 +291,8 @@ class MoveFromTo<bits<6> func, string instr_asm>: class CountLeading<bits<6> func, string instr_asm>: FR< 0x1c, func, - (ops CPURegs:$dst, CPURegs:$src), + (outs CPURegs:$dst), + (ins CPURegs:$src), !strconcat(instr_asm, " $dst, $src"), []>; @@ -279,18 +301,18 @@ class CountLeading<bits<6> func, string instr_asm>: // Pseudo instructions //===----------------------------------------------------------------------===// -class Pseudo<dag ops, string asmstr, list<dag> pattern>: - MipsInst<ops, asmstr, pattern>; +class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: + MipsInst<outs, ins, asmstr, pattern>; // As stack alignment is always done with addiu, we need a 16-bit immediate -def ADJCALLSTACKDOWN : Pseudo<(ops uimm16:$amt), +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins uimm16:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>, Imp<[SP],[SP]>; -def ADJCALLSTACKUP : Pseudo<(ops uimm16:$amt), +def ADJCALLSTACKUP : Pseudo<(outs), (ins uimm16:$amt), "!ADJCALLSTACKUP $amt", [(callseq_end imm:$amt)]>, Imp<[SP],[SP]>; -def IMPLICIT_DEF_CPURegs : Pseudo<(ops CPURegs:$dst), +def IMPLICIT_DEF_CPURegs : Pseudo<(outs CPURegs:$dst), (ins), "!IMPLICIT_DEF $dst", [(set CPURegs:$dst, (undef))]>; @@ -381,14 +403,14 @@ def CLZ : CountLeading<0x20, "clz">; // No operation let addr=0 in -def NOOP : FJ<0, (ops), "nop", []>; +def NOOP : FJ<0, (outs), (ins), "nop", []>; // Ret instruction - as mips does not have "ret" a // jr $ra must be generated. let isReturn=1, isTerminator=1, hasDelaySlot=1, noResults=1, isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in { - def RET : FR <0x00, 0x02, (ops CPURegs:$target), + def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target), "jr $target", [(MipsRet CPURegs:$target)]>; } diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index c7a87ca5b6..42e82bf525 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -116,7 +116,7 @@ foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const /// Mips Callee Saved Registers const unsigned* MipsRegisterInfo:: -getCalleeSavedRegs() const +getCalleeSavedRegs(const MachineFunction *MF) const { // Mips calle-save register range is $16-$26(s0-s7) static const unsigned CalleeSavedRegs[] = { @@ -128,7 +128,7 @@ getCalleeSavedRegs() const /// Mips Callee Saved Register Classes const TargetRegisterClass* const* -MipsRegisterInfo::getCalleeSavedRegClasses() const +MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { static const TargetRegisterClass * const CalleeSavedRegClasses[] = { &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index d84194f31a..ebc0318b88 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -49,9 +49,10 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { const TargetRegisterClass *RC) const; - const unsigned *getCalleeSavedRegs() const; + const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; - const TargetRegisterClass* const* getCalleeSavedRegClasses() const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction* MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index a7e25cf990..e20ea47652 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -57,7 +57,7 @@ def HI48_64 : SDNodeXForm<imm, [{ // Pseudo instructions. // -def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD", +def IMPLICIT_DEF_G8RC : Pseudo<(outs G8RC:$rD), (ins),"; IMPLICIT_DEF_G8RC $rD", [(set G8RC:$rD, (undef))]>; @@ -66,7 +66,7 @@ def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD", // let Defs = [LR8] in - def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>, + def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, PPC970_Unit_BRU; // Macho ABI Calls. @@ -79,11 +79,11 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL8_Macho : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA8_Macho : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>; } @@ -98,11 +98,11 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL8_ELF : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA8_ELF : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>; } @@ -121,22 +121,26 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), //===----------------------------------------------------------------------===// // 64-bit SPR manipulation instrs. -def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>, +def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), + "mfctr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; let Pattern = [(PPCmtctr G8RC:$rS)] in { -def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>, +def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), + "mtctr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } -def DYNALLOC8 : Pseudo<(ops G8RC:$result, G8RC:$negsize, memri:$fpsi), +def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi), "${:comment} DYNALLOC8 $result, $negsize, $fpsi", [(set G8RC:$result, (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>, Imp<[X1],[X1]>; -def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>, +def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), + "mtlr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; -def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>, +def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), + "mflr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; @@ -147,187 +151,187 @@ def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>, let PPC970_Unit = 1 in { // FXU Operations. // Copies, extends, truncates. -def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), +def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), "or $rA, $rS, $rB", IntGeneral, []>; -def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), +def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), "or $rA, $rS, $rB", IntGeneral, []>; -def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm), +def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), "li $rD, $imm", IntGeneral, [(set G8RC:$rD, immSExt16:$imm)]>; -def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm), +def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), "lis $rD, $imm", IntGeneral, [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; // Logical ops. -def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "nand $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; -def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "and $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; -def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "andc $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; -def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "or $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; -def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "nor $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; -def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "orc $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; -def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "eqv $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; -def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "xor $rA, $rS, $rB", IntGeneral, [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; // Logical ops with immediate. -def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "andi. $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, isDOT; -def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "andis. $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, isDOT; -def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "ori $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; -def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "oris $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; -def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "xori $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; -def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), +def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "xoris $dst, $src1, $src2", IntGeneral, [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; -def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "add $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; -def ADDC8 : XOForm_1<31, 10, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "addc $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, PPC970_DGroup_Cracked; -def ADDE8 : XOForm_1<31, 138, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "adde $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; -def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm), +def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), "addi $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; -def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm), +def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), "addis $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; -def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm), +def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), "subfic $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; -def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "subf $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; -def SUBFC8 : XOForm_1<31, 8, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "subfc $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, PPC970_DGroup_Cracked; -def SUBFE8 : XOForm_1<31, 136, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "subfe $rT, $rA, $rB", IntGeneral, [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; -def ADDME8 : XOForm_3<31, 234, 0, (ops G8RC:$rT, G8RC:$rA), +def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), "addme $rT, $rA", IntGeneral, [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>; -def ADDZE8 : XOForm_3<31, 202, 0, (ops G8RC:$rT, G8RC:$rA), +def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), "addze $rT, $rA", IntGeneral, [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; -def NEG8 : XOForm_3<31, 104, 0, (ops G8RC:$rT, G8RC:$rA), +def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), "neg $rT, $rA", IntGeneral, [(set G8RC:$rT, (ineg G8RC:$rA))]>; -def SUBFME8 : XOForm_3<31, 232, 0, (ops G8RC:$rT, G8RC:$rA), +def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), "subfme $rT, $rA", IntGeneral, [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>; -def SUBFZE8 : XOForm_3<31, 200, 0, (ops G8RC:$rT, G8RC:$rA), +def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), "subfze $rT, $rA", IntGeneral, [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; -def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "mulhd $rT, $rA, $rB", IntMulHW, [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; -def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "mulhdu $rT, $rA, $rB", IntMulHWU, [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; -def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB), +def CMPD : XForm_16_ext<31, 0, (outs), (ins CRRC:$crD, G8RC:$rA, G8RC:$rB), "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; -def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB), +def CMPLD : XForm_16_ext<31, 32, (outs), (ins CRRC:$crD, G8RC:$rA, G8RC:$rB), "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; -def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm), +def CMPDI : DForm_5_ext<11, (outs), (ins CRRC:$crD, G8RC:$rA, s16imm:$imm), "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; -def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2), +def CMPLDI : DForm_6_ext<10, (outs), (ins CRRC:$dst, G8RC:$src1, u16imm:$src2), "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; -def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), +def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "sld $rA, $rS, $rB", IntRotateD, [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64; -def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), +def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "srd $rA, $rS, $rB", IntRotateD, [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64; -def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), +def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "srad $rA, $rS, $rB", IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64; -def EXTSB8 : XForm_11<31, 954, (ops G8RC:$rA, G8RC:$rS), +def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), "extsb $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; -def EXTSH8 : XForm_11<31, 922, (ops G8RC:$rA, G8RC:$rS), +def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), "extsh $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; -def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), +def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), "extsw $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. -def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), +def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), "extsw $rA, $rS", IntGeneral, [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; -def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS), +def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), "extsw $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; -def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH), +def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), "sradi $rA, $rS, $SH", IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; -def CNTLZD : XForm_11<31, 58, (ops G8RC:$rA, G8RC:$rS), +def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), "cntlzd $rA, $rS", IntGeneral, [(set G8RC:$rA, (ctlz G8RC:$rS))]>; -def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "divd $rT, $rA, $rB", IntDivD, [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "divdu $rT, $rA, $rB", IntDivD, [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), +def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), "mulld $rT, $rA, $rB", IntMulHD, [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; let isCommutable = 1 in { def RLDIMI : MDForm_1<30, 3, - (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), + (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), "rldimi $rA, $rS, $SH, $MB", IntRotateD, []>, isPPC64, RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; @@ -335,11 +339,11 @@ def RLDIMI : MDForm_1<30, 3, // Rotate instructions. def RLDICL : MDForm_1<30, 0, - (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), + (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), "rldicl $rA, $rS, $SH, $MB", IntRotateD, []>, isPPC64; def RLDICR : MDForm_1<30, 1, - (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), + (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), "rldicr $rA, $rS, $SH, $ME", IntRotateD, []>, isPPC64; } // End FXU Operations. @@ -352,25 +356,25 @@ def RLDICR : MDForm_1<30, 1, // Sign extending loads. let isLoad = 1, PPC970_Unit = 2 in { -def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src), +def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), "lha $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; -def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src), +def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), "lwa $rD, $src", LdStLWA, [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; -def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src), +def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), "lhax $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; -def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), +def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), "lwax $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; // Update forms. -def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp, +def LHAU8 : DForm_1<43, (outs G8RC:$rD), (ins ptr_rc:$ea_result, symbolLo:$disp, ptr_rc:$rA), "lhau $rD, $disp($rA)", LdStGeneral, []>, RegConstraint<"$rA = $ea_result">, @@ -381,37 +385,37 @@ def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp, // Zero extending loads. let isLoad = 1, PPC970_Unit = 2 in { -def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src), +def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; -def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src), +def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), "lhz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; -def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src), +def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), "lwz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; -def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src), +def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), "lbzx $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; -def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src), +def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), "lhzx $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; -def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src), +def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), "lwzx $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; // Update forms. -def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LBZU8 : DForm_1<35, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lbzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LHZU8 : DForm_1<41, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lhzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LWZU8 : DForm_1<33, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lwzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; @@ -420,14 +424,14 @@ def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr), // Full 8-byte loads. let isLoad = 1, PPC970_Unit = 2 in { -def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src), +def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), "ld $rD, $src", LdStLD, [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; -def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), +def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), "ldx $rD, $src", LdStLD, [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; -def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr), +def LDU : DSForm_1<58, 1, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memrix:$addr), "ldu $rD, $addr", LdStLD, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, NoEncode<"$ea_result">; @@ -436,32 +440,32 @@ def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr), let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Truncating stores. -def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src), +def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), "stb $rS, $src", LdStGeneral, [(truncstorei8 G8RC:$rS, iaddr:$src)]>; -def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src), +def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), "sth $rS, $src", LdStGeneral, [(truncstorei16 G8RC:$rS, iaddr:$src)]>; -def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src), +def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), "stw $rS, $src", LdStGeneral, [(truncstorei32 G8RC:$rS, iaddr:$src)]>; -def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst), +def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), "stbx $rS, $dst", LdStGeneral, [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst), +def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), "sthx $rS, $dst", LdStGeneral, [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst), +def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), "stwx $rS, $dst", LdStGeneral, [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; // Normal 8-byte stores. -def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst), +def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), "std $rS, $dst", LdStSTD, [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; -def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst), +def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), "stdx $rS, $dst", LdStSTD, [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, PPC970_DGroup_Cracked; @@ -469,21 +473,21 @@ def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst), let isStore = 1, PPC970_Unit = 2 in { -def STBU8 : DForm_1<38, (ops ptr_rc:$ea_res, G8RC:$rS, +def STBU8 : DForm_1<38, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stbu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STHU8 : DForm_1<45, (ops ptr_rc:$ea_res, G8RC:$rS, +def STHU8 : DForm_1<45, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "sthu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS, +def STWU8 : DForm_1<37, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stwu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, @@ -491,7 +495,7 @@ def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS, +def STDU : DSForm_1<62, 1, (outs), (ins ptr_rc:$ea_res, G8RC:$rS, s16immX4:$ptroff, ptr_rc:$ptrreg), "stdu $rS, $ptroff($ptrreg)", LdStSTD, [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, @@ -503,16 +507,16 @@ def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS, let isStore = 1, noResults = 1, PPC970_Unit = 2 in { -def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst), +def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), "stdux $rS, $dst", LdStSTD, []>, isPPC64; // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. -def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst), +def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), "std $rT, $dst", LdStSTD, [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; -def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), +def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), "stdx $rT, $dst", LdStSTD, [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, PPC970_DGroup_Cracked; @@ -526,10 +530,10 @@ def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), let PPC970_Unit = 3 in { // FPU Operations. -def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), +def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), "fcfid $frD, $frB", FPGeneral, [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; -def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), +def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), "fctidz $frD, $frB", FPGeneral, [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; } diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 8a2f255c8e..47a470c1de 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -138,97 +138,97 @@ def vecspltisw : PatLeaf<(build_vector), [{ // VA1a_Int - A VAForm_1a intrinsic definition. class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> - : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), + : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; // VX1_Int - A VXForm_1 intrinsic definition. class VX1_Int<bits<11> xo, string opc, Intrinsic IntID> - : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), !strconcat(opc, " $vD, $vA, $vB"), VecFP, [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; // VX2_Int - A VXForm_2 intrinsic definition. class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> - : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), + : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), !strconcat(opc, " $vD, $vB"), VecFP, [(set VRRC:$vD, (IntID VRRC:$vB))]>; //===----------------------------------------------------------------------===// // Instruction Definitions. -def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; IMPLICIT_DEF_VRRC $rD", +def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD", [(set VRRC:$rD, (v4i32 (undef)))]>; let noResults = 1 in { -def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), +def DSS : DSS_Form<822, (outs), (ins u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), "dss $STRM, $A", LdStGeneral /*FIXME*/, []>; -def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), +def DST : DSS_Form<342, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; -def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), +def DSTST : DSS_Form<374, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; } -def MFVSCR : VXForm_4<1540, (ops VRRC:$vD), +def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), "mfvcr $vD", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; -def MTVSCR : VXForm_5<1604, (ops VRRC:$vB), +def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), "mtvcr $vB", LdStGeneral, [(int_ppc_altivec_mtvscr VRRC:$vB)]>; let isLoad = 1, PPC970_Unit = 2 in { // Loads. -def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src), +def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), "lvebx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; -def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src), +def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), "lvehx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; -def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src), +def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), "lvewx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; -def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src), +def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), "lvx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; -def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src), +def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), "lvxl $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; } -def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src), +def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), "lvsl $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, PPC970_Unit_LSU; -def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src), +def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), "lvsr $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, PPC970_Unit_LSU; let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores. -def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst), +def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), "stvebx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>; -def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst), +def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), "stvehx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>; -def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst), +def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), "stvewx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>; -def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst), +def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), "stvx $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>; -def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst), +def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), "stvxl $rS, $dst", LdStGeneral, [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>; } let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. -def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), +def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), "vmaddfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB))]>, Requires<[FPContractions]>; -def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), +def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), "vnmsubfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB)))]>, @@ -241,24 +241,24 @@ def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; // Shuffles. -def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), +def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), "vsldoi $vD, $vA, $vB, $SH", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VSLDOI_shuffle_mask:$SH))]>; // VX-Form instructions. AltiVec arithmetic ops. -def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vaddfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; -def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vaddubm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; -def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vadduhm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; -def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vadduwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -271,26 +271,26 @@ def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; -def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vand $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vandc $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>; -def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; -def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vcfux $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; -def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vctsxs $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; -def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vctuxs $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; @@ -319,27 +319,27 @@ def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; -def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrghb $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGHB_shuffle_mask))]>; -def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrghh $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGHH_shuffle_mask))]>; -def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrghw $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGHW_shuffle_mask))]>; -def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrglb $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGLB_shuffle_mask))]>; -def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrglh $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGLH_shuffle_mask))]>; -def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vmrglw $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VMRGLW_shuffle_mask))]>; @@ -369,16 +369,16 @@ def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; -def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; -def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsububm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; -def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsubuhm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; -def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vsubuwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -394,13 +394,13 @@ def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>; def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>; def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>; -def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vnor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>; -def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vxor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -414,15 +414,15 @@ def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; -def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), VSPLTB_shuffle_mask:$UIMM))]>; -def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), VSPLTH_shuffle_mask:$UIMM))]>; -def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), VSPLTW_shuffle_mask:$UIMM))]>; @@ -437,13 +437,13 @@ def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>; def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>; -def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM), +def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), "vspltisb $vD, $SIMM", VecPerm, [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; -def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM), +def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), "vspltish $vD, $SIMM", VecPerm, [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; -def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM), +def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), "vspltisw $vD, $SIMM", VecPerm, [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; @@ -453,12 +453,12 @@ def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>; def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>; def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>; def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>; -def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vpkuhum $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VPKUHUM_shuffle_mask))]>; def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; -def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), "vpkuwum $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, VPKUWUM_shuffle_mask))]>; @@ -476,10 +476,10 @@ def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; // Altivec Comparisons. class VCMP<bits<10> xo, string asmstr, ValueType Ty> - : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare, + : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; class VCMPo<bits<10> xo, string asmstr, ValueType Ty> - : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare, + : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { let Defs = [CR6]; let RC = 1; @@ -519,7 +519,7 @@ def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; -def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), +def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), "vxor $vD, $vD, $vD", VecFP, [(set VRRC:$vD, (v4i32 immAllZerosV))]>; } diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 6a4a59b593..865320c1d6 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -11,7 +11,7 @@ // // PowerPC instruction formats -class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> +class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : Instruction { field bits<32> Inst; @@ -20,7 +20,8 @@ class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> let Name = ""; let Namespace = "PPC"; let Inst{0-5} = opcode; - let OperandList = OL; + let OutOperandList = OOL; + let InOperandList = IOL; let AsmString = asmstr; let Itinerary = itin; @@ -48,9 +49,9 @@ class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } // 1.7.1 I-Form -class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr, +class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { let Pattern = pattern; bits<24> LI; @@ -60,8 +61,8 @@ class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr, } // 1.7.2 B-Form -class BForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr> - : I<opcode, OL, asmstr, BrB> { +class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> + : I<opcode, OOL, IOL, asmstr, BrB> { bits<7> BIBO; // 2 bits of BI and 5 bits of BO. bits<3> CR; bits<14> BD; @@ -79,9 +80,9 @@ class BForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr> // 1.7.4 D-Form -class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> B; bits<16> C; @@ -93,9 +94,9 @@ class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = C; } -class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<16> C; bits<5> B; @@ -107,13 +108,13 @@ class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = C; } -class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : DForm_base<opcode, OL, asmstr, itin, pattern>; +class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>; -class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<16> B; @@ -124,9 +125,9 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = B; } -class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : I<opcode, OL, asmstr, itin> { +class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> B; bits<5> A; bits<16> C; @@ -138,16 +139,17 @@ class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, let Inst{16-31} = C; } -class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, - list<dag> pattern> - : DForm_1<opcode, OL, asmstr, itin, pattern> { +class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { let A = 0; let B = 0; let C = 0; } -class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { +class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<1> L; bits<5> RA; @@ -160,24 +162,27 @@ class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> let Inst{16-31} = I; } -class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : DForm_5<opcode, OL, asmstr, itin> { +class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : DForm_5<opcode, OOL, IOL, asmstr, itin> { let L = PPC64; } -class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : DForm_5<opcode, OL, asmstr, itin>; +class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : DForm_5<opcode, OOL, IOL, asmstr, itin>; -class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> - : DForm_6<opcode, OL, asmstr, itin> { +class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : DForm_6<opcode, OOL, IOL, asmstr, itin> { let L = PPC64; } // 1.7.5 DS-Form -class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr, +class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RST; bits<14> DS; bits<5> RA; @@ -191,9 +196,9 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr, } // 1.7.6 X-Form -class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RST; bits<5> A; bits<5> B; @@ -212,9 +217,9 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr, // This is the same as XForm_base_r3xo, but the first two operands are swapped // when code is emitted. class XForm_base_r3xo_swapped - <bits<6> opcode, bits<10> xo, dag OL, string asmstr, + <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> RST; bits<5> B; @@ -229,36 +234,36 @@ class XForm_base_r3xo_swapped } -class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>; + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; -class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { let Pattern = pattern; } -class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>; + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; -class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { let Pattern = pattern; } -class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { let B = 0; let Pattern = pattern; } -class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<1> L; bits<5> RA; @@ -273,15 +278,15 @@ class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : XForm_16<opcode, xo, OL, asmstr, itin> { + : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { let L = PPC64; } -class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<5> FRA; bits<5> FRB; @@ -294,26 +299,26 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { } -class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { let A = 0; } -class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { } // DCB_Form - Form X instruction, used for dcb* instructions. -class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, +class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<31, OL, asmstr, itin> { + : I<31, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> B; @@ -328,9 +333,9 @@ class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, // DSS_Form - Form X instruction, used for altivec dss* instructions. -class DSS_Form<bits<10> xo, dag OL, string asmstr, +class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<31, OL, asmstr, itin> { + : I<31, OOL, IOL, asmstr, itin> { bits<1> T; bits<2> STRM; bits<5> A; @@ -348,9 +353,9 @@ class DSS_Form<bits<10> xo, dag OL, string asmstr, } // 1.7.7 XL-Form -class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> CRD; bits<5> CRA; bits<5> CRB; @@ -364,9 +369,9 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> CRD; let Pattern = pattern; @@ -378,9 +383,9 @@ class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, +class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> BO; bits<5> BI; bits<2> BH; @@ -396,8 +401,8 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, } class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, - dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { bits<7> BIBO; // 2 bits of BI and 5 bits of BO. bits<3> CR; @@ -409,16 +414,16 @@ class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, - dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { let BO = bo; let BI = bi; let BH = 0; } -class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<3> BF; bits<3> BFA; @@ -432,9 +437,9 @@ class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, } // 1.7.8 XFX-Form -class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RT; bits<10> SPR; @@ -454,14 +459,14 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, } class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, - dag OL, string asmstr, InstrItinClass itin> - : XFXForm_1<opcode, xo, OL, asmstr, itin> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin> + : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { let SPR = spr; } -class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RT; let Inst{6-10} = RT; @@ -470,9 +475,9 @@ class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<8> FXM; bits<5> ST; @@ -484,9 +489,9 @@ class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> ST; bits<8> FXM; @@ -498,20 +503,20 @@ class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } -class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr, +class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : XFXForm_1<opcode, xo, OL, asmstr, itin>; + : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, - dag OL, string asmstr, InstrItinClass itin> - : XFXForm_7<opcode, xo, OL, asmstr, itin> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin> + : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { let SPR = spr; } // 1.7.10 XS-Form - SRADI. -class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr, +class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> A; bits<5> RS; bits<6> SH; @@ -528,9 +533,9 @@ class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr, } // 1.7.11 XO-Form -class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, +class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RT; bits<5> RA; bits<5> RB; @@ -548,15 +553,15 @@ class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, } class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, - dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> - : XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> { + dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { let RB = 0; } // 1.7.12 A-Form -class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, +class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> FRT; bits<5> FRA; bits<5> FRC; @@ -574,22 +579,22 @@ class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, let Inst{31} = RC; } -class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, +class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { + : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { let FRC = 0; } -class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, +class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { + : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { let FRB = 0; } // 1.7.13 M-Form -class MForm_1<bits<6> opcode, dag OL, string asmstr, +class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RA; bits<5> RS; bits<5> RB; @@ -608,15 +613,15 @@ class MForm_1<bits<6> opcode, dag OL, string asmstr, let Inst{31} = RC; } -class MForm_2<bits<6> opcode, dag OL, string asmstr, +class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : MForm_1<opcode, OL, asmstr, itin, pattern> { + : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { } // 1.7.14 MD-Form -class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, +class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<opcode, OL, asmstr, itin> { + : I<opcode, OOL, IOL, asmstr, itin> { bits<5> RA; bits<5> RS; bits<6> SH; @@ -640,9 +645,9 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, // E-1 VA-Form // VAForm_1 - DACB ordering. -class VAForm_1<bits<6> xo, dag OL, string asmstr, +class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VC; @@ -658,9 +663,9 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr, } // VAForm_1a - DABC ordering. -class VAForm_1a<bits<6> xo, dag OL, string asmstr, +class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -675,9 +680,9 @@ class VAForm_1a<bits<6> xo, dag OL, string asmstr, let Inst{26-31} = xo; } -class VAForm_2<bits<6> xo, dag OL, string asmstr, +class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -694,9 +699,9 @@ class VAForm_2<bits<6> xo, dag OL, string asmstr, } // E-2 VX-Form -class VXForm_1<bits<11> xo, dag OL, string asmstr, +class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -709,17 +714,17 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr, let Inst{21-31} = xo; } -class VXForm_setzero<bits<11> xo, dag OL, string asmstr, +class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : VXForm_1<xo, OL, asmstr, itin, pattern> { + : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { let VA = VD; let VB = VD; } -class VXForm_2<bits<11> xo, dag OL, string asmstr, +class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VB; @@ -731,9 +736,9 @@ class VXForm_2<bits<11> xo, dag OL, string asmstr, let Inst{21-31} = xo; } -class VXForm_3<bits<11> xo, dag OL, string asmstr, +class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> IMM; @@ -746,9 +751,9 @@ class VXForm_3<bits<11> xo, dag OL, string asmstr, } /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. -class VXForm_4<bits<11> xo, dag OL, string asmstr, +class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; let Pattern = pattern; @@ -760,9 +765,9 @@ class VXForm_4<bits<11> xo, dag OL, string asmstr, } /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. -class VXForm_5<bits<11> xo, dag OL, string asmstr, +class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VB; let Pattern = pattern; @@ -774,9 +779,9 @@ class VXForm_5<bits<11> xo, dag OL, string asmstr, } // E-4 VXR-Form -class VXRForm_1<bits<10> xo, dag OL, string asmstr, +class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> - : I<4, OL, asmstr, itin> { + : I<4, OOL, IOL, asmstr, itin> { bits<5> VD; bits<5> VA; bits<5> VB; @@ -792,8 +797,8 @@ class VXRForm_1<bits<10> xo, dag OL, string asmstr, } //===----------------------------------------------------------------------===// -class Pseudo<dag OL, string asmstr, list<dag> pattern> - : I<0, OL, asmstr, NoItinerary> { +class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> + : I<0, OOL, IOL, asmstr, NoItinerary> { let PPC64 = 0; let Pattern = pattern; let Inst{31-0} = 0; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index fe18978400..499f537cff 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -297,69 +297,72 @@ def FPContractions : Predicate<"!NoExcessFPPrecision">; // Pseudo-instructions: let hasCtrlDep = 1 in { -def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "${:comment} ADJCALLSTACKDOWN", [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>; -def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), +def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt), "${:comment} ADJCALLSTACKUP", [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>; -def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), +def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), "UPDATE_VRSAVE $rD, $rS", []>; } -def DYNALLOC : Pseudo<(ops GPRC:$result, GPRC:$negsize, memri:$fpsi), +def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "${:comment} DYNALLOC $result, $negsize, $fpsi", [(set GPRC:$result, (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>, Imp<[R1],[R1]>; -def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD", +def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins), + "${:comment}IMPLICIT_DEF_GPRC $rD", [(set GPRC:$rD, (undef))]>; -def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD", +def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins), + "${:comment} IMPLICIT_DEF_F8 $rD", [(set F8RC:$rD, (undef))]>; -def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD", +def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins), + "${:comment} IMPLICIT_DEF_F4 $rD", [(set F4RC:$rD, (undef))]>; // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the // scheduler into a branch sequence. let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. PPC970_Single = 1 in { - def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F, + def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F, + def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F, + def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, + def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; - def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, + def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", []>; } let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in { let isReturn = 1 in - def BLR : XLForm_2_br<19, 16, 0, (ops pred:$p), + def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), "b${p:cc}lr ${p:reg}", BrB, [(retflag)]>; - def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; + def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; } let Defs = [LR] in - def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>, + def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, PPC970_Unit_BRU; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1, PPC970_Unit = 7 in { let isBarrier = 1 in { - def B : IForm<18, 0, 0, (ops target:$dst), + def B : IForm<18, 0, 0, (outs), (ins target:$dst), "b $dst", BrB, [(br bb:$dst)]>; } @@ -367,7 +370,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, // BCC represents an arbitrary conditional branch on a predicate. // FIXME: should be able to write a pattern for PPCcondbranch, but can't use // a two-value operand where a dag node expects two operands. :( - def BCC : BForm<16, 0, 0, (ops pred:$cond, target:$dst), + def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), "b${cond:cc} ${cond:reg}, $dst" /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; } @@ -382,13 +385,13 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL_Macho : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA_Macho : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>; def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1, - (ops variable_ops), + (outs), (ins variable_ops), "bctrl", BrB, [(PPCbctrl_Macho)]>; } @@ -403,41 +406,41 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL_ELF : IForm<18, 0, 1, - (ops calltarget:$func, variable_ops), + (outs), (ins calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA_ELF : IForm<18, 1, 1, - (ops aaddr:$func, variable_ops), + (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_ELF (i32 imm:$func))]>; def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1, - (ops variable_ops), + (outs), (ins variable_ops), "bctrl", BrB, [(PPCbctrl_ELF)]>; } // DCB* instructions. -def DCBA : DCB_Form<758, 0, (ops memrr:$dst), +def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBF : DCB_Form<86, 0, (ops memrr:$dst), +def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBI : DCB_Form<470, 0, (ops memrr:$dst), +def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBST : DCB_Form<54, 0, (ops memrr:$dst), +def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBT : DCB_Form<278, 0, (ops memrr:$dst), +def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBTST : DCB_Form<246, 0, (ops memrr:$dst), +def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst), +def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), +def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; @@ -447,55 +450,55 @@ def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), // Unindexed (r+i) Loads. let isLoad = 1, PPC970_Unit = 2 in { -def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), +def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; -def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), +def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), "lha $rD, $src", LdStLHA, [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; -def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), +def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), "lhz $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; -def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), +def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), "lwz $rD, $src", LdStGeneral, [(set GPRC:$rD, (load iaddr:$src))]>; -def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src), +def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), "lfs $rD, $src", LdStLFDU, [(set F4RC:$rD, (load iaddr:$src))]>; -def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src), +def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), "lfd $rD, $src", LdStLFD, [(set F8RC:$rD, (load iaddr:$src))]>; // Unindexed (r+i) Loads with Update (preinc). -def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LBZU : DForm_1<35, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lbzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LHAU : DForm_1<43, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lhau $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LHZU : DForm_1<41, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lhzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr), +def LWZU : DForm_1<33, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lwzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LFSU : DForm_1<49, (outs F4RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lfs $rD, $addr", LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr), +def LFDU : DForm_1<51, (outs F8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr), "lfd $rD, $addr", LdStLFD, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; @@ -504,32 +507,32 @@ def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr), // Indexed (r+r) Loads. // let isLoad = 1, PPC970_Unit = 2 in { -def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), +def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), "lbzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; -def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), +def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), "lhax $rD, $src", LdStLHA, [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; -def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), +def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), "lhzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; -def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), +def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), "lwzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (load xaddr:$src))]>; -def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src), +def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), "lhbrx $rD, $src", LdStGeneral, [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; -def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src), +def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), "lwbrx $rD, $src", LdStGeneral, [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; -def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src), +def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), "lfsx $frD, $src", LdStLFDU, [(set F4RC:$frD, (load xaddr:$src))]>; -def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), +def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), "lfdx $frD, $src", LdStLFDU, [(set F8RC:$frD, (load xaddr:$src))]>; } @@ -540,52 +543,52 @@ def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src), // Unindexed (r+i) Stores. let isStore = 1, noResults = 1, PPC970_Unit = 2 in { -def STB : DForm_1<38, (ops GPRC:$rS, memri:$src), +def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), "stb $rS, $src", LdStGeneral, [(truncstorei8 GPRC:$rS, iaddr:$src)]>; -def STH : DForm_1<44, (ops GPRC:$rS, memri:$src), +def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), "sth $rS, $src", LdStGeneral, [(truncstorei16 GPRC:$rS, iaddr:$src)]>; -def STW : DForm_1<36, (ops GPRC:$rS, memri:$src), +def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), "stw $rS, $src", LdStGeneral, [(store GPRC:$rS, iaddr:$src)]>; -def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst), +def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), "stfs $rS, $dst", LdStUX, [(store F4RC:$rS, iaddr:$dst)]>; -def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst), +def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), "stfd $rS, $dst", LdStUX, [(store F8RC:$rS, iaddr:$dst)]>; } // Unindexed (r+i) Stores with Update (preinc). let isStore = 1, PPC970_Unit = 2 in { -def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, +def STBU : DForm_1<39, (outs), (ins ptr_rc:$ea_res, GPRC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stbu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STHU : DForm_1<45, (ops ptr_rc:$ea_res, GPRC:$rS, +def STHU : DForm_1<45, (outs), (ins ptr_rc:$ea_res, GPRC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "sthu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, +def STWU : DForm_1<37, (outs), (ins ptr_rc:$ea_res, GPRC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stwu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, +def STFSU : DForm_1<37, (outs), (ins ptr_rc:$ea_res, F4RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff))]>, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; -def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, +def STFDU : DForm_1<37, (outs), (ins ptr_rc:$ea_res, F8RC:$rS, symbolLo:$ptroff, ptr_rc:$ptrreg), "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, @@ -597,37 +600,37 @@ def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, // Indexed (r+r) Stores. // let isStore = 1, noResults = 1, PPC970_Unit = 2 in { -def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst), +def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), "stbx $rS, $dst", LdStGeneral, [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst), +def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), "sthx $rS, $dst", LdStGeneral, [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst), +def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), "stwx $rS, $dst", LdStGeneral, [(store GPRC:$rS, xaddr:$dst)]>, PPC970_DGroup_Cracked; -def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), +def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), "stwux $rS, $rA, $rB", LdStGeneral, []>; -def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst), +def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), "sthbrx $rS, $dst", LdStGeneral, [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, PPC970_DGroup_Cracked; -def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst), +def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), "stwbrx $rS, $dst", LdStGeneral, [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, PPC970_DGroup_Cracked; -def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), +def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), "stfiwx $frS, $dst", LdStUX, [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; -def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), +def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), "stfsx $frS, $dst", LdStUX, [(store F4RC:$frS, xaddr:$dst)]>; -def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), +def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), "stfdx $frS, $dst", LdStUX, [(store F8RC:$frS, xaddr:$dst)]>; } @@ -638,140 +641,140 @@ def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst), // let PPC970_Unit = 1 in { // FXU Operations. -def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addi $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; -def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, PPC970_DGroup_Cracked; -def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral, []>; -def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), +def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), "addis $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; -def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), +def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), "la $rD, $sym($rA)", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, (PPClo tglobaladdr:$sym, 0)))]>; -def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "mulli $rD, $rA, $imm", IntMulLI, [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; -def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), +def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "subfic $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; -def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), +def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), "li $rD, $imm", IntGeneral, [(set GPRC:$rD, immSExt16:$imm)]>; -def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), +def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), "lis $rD, $imm", IntGeneral, [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; } let PPC970_Unit = 1 in { // FXU Operations. -def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "andi. $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, isDOT; -def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "andis. $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, isDOT; -def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "ori $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; -def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "oris $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; -def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "xori $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; -def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), +def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), "xoris $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; -def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral, +def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, []>; -def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), +def CMPWI : DForm_5_ext<11, (outs), (ins CRRC:$crD, GPRC:$rA, s16imm:$imm), "cmpwi $crD, $rA, $imm", IntCompare>; -def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), +def CMPLWI : DForm_6_ext<10, (outs), (ins CRRC:$dst, GPRC:$src1, u16imm:$src2), "cmplwi $dst, $src1, $src2", IntCompare>; } let PPC970_Unit = 1 in { // FXU Operations. -def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "nand $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; -def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "and $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; -def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "andc $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; -def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "or $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; -def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "nor $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; -def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "orc $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; -def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "eqv $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; -def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "xor $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; -def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "slw $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; -def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "srw $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; -def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), +def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), "sraw $rA, $rS, $rB", IntShift, [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; } let PPC970_Unit = 1 in { // FXU Operations. -def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), +def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), "srawi $rA, $rS, $SH", IntShift, [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; -def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS), +def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), "cntlzw $rA, $rS", IntGeneral, [(set GPRC:$rA, (ctlz GPRC:$rS))]>; -def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS), +def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), "extsb $rA, $rS", IntGeneral, [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; -def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS), +def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), "extsh $rA, $rS", IntGeneral, [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; -def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), +def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), "cmpw $crD, $rA, $rB", IntCompare>; -def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), +def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), "cmplw $crD, $rA, $rB", IntCompare>; } let PPC970_Unit = 3 in { // FPU Operations. -//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), +//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), // "fcmpo $crD, $fA, $fB", FPCompare>; -def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB), +def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), "fcmpu $crD, $fA, $fB", FPCompare>; -def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB), +def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), "fcmpu $crD, $fA, $fB", FPCompare>; -def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB), +def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), "fctiwz $frD, $frB", FPGeneral, [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; -def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB), +def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), "frsp $frD, $frB", FPGeneral, [(set F4RC:$frD, (fround F8RC:$frB))]>; -def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB), +def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), "fsqrt $frD, $frB", FPSqrt, [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; -def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), +def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), "fsqrts $frD, $frB", FPSqrt, [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; } @@ -782,37 +785,37 @@ def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), /// often coalesced away and we don't want the dispatch group builder to think /// that they will fill slots (which could cause the load of a LSU reject to /// sneak into a d-group with a store). -def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), +def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), "fmr $frD, $frB", FPGeneral, []>, // (set F4RC:$frD, F4RC:$frB) PPC970_Unit_Pseudo; -def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB), +def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB), "fmr $frD, $frB", FPGeneral, []>, // (set F8RC:$frD, F8RC:$frB) PPC970_Unit_Pseudo; -def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB), +def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), "fmr $frD, $frB", FPGeneral, [(set F8RC:$frD, (fextend F4RC:$frB))]>, PPC970_Unit_Pseudo; let PPC970_Unit = 3 in { // FPU Operations. // These are artificially split into two different forms, for 4/8 byte FP. -def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB), +def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), "fabs $frD, $frB", FPGeneral, [(set F4RC:$frD, (fabs F4RC:$frB))]>; -def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB), +def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), "fabs $frD, $frB", FPGeneral, [(set F8RC:$frD, (fabs F8RC:$frB))]>; -def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB), +def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), "fnabs $frD, $frB", FPGeneral, [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; -def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB), +def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), "fnabs $frD, $frB", FPGeneral, [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; -def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB), +def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), "fneg $frD, $frB", FPGeneral, [(set F4RC:$frD, (fneg F4RC:$frB))]>; -def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), +def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), "fneg $frD, $frB", FPGeneral, [(set F8RC:$frD, (fneg F8RC:$frB))]>; } @@ -820,48 +823,52 @@ def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), // XL-Form instructions. condition register logical ops. // -def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), +def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), "mcrf $BF, $BFA", BrMCR>, PPC970_DGroup_First, PPC970_Unit_CRU; -def CREQV : XLForm_1<19, 289, (ops CRRC:$CRD, CRRC:$CRA, CRRC:$CRB), +def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB), "creqv $CRD, $CRA, $CRB", BrCR, []>; -def SETCR : XLForm_1_ext<19, 289, (ops CRRC:$dst), +def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins), "creqv $dst, $dst, $dst", BrCR, []>; // XFX-Form instructions. Instructions that deal with SPRs. // -def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, +def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), + "mfctr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; let Pattern = [(PPCmtctr GPRC:$rS)] in { -def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, +def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), + "mtctr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } -def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, +def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), + "mtlr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; -def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, +def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), + "mflr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like // a GPR on the PPC970. As such, copies in and out have the same performance // characteristics as an OR instruction. -def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), +def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), "mtspr 256, $rS", IntGeneral>, PPC970_DGroup_Single, PPC970_Unit_FXU; -def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), +def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), "mfspr $rT, 256", IntGeneral>, PPC970_DGroup_First, PPC970_Unit_FXU; -def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), +def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; -def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, +def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; -def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), +def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), "mfcr $rT, $FXM", SprMFCR>, PPC970_DGroup_First, PPC970_Unit_CRU; @@ -869,56 +876,56 @@ let PPC970_Unit = 1 in { // FXU Operations. // XO-Form instructions. Arithmetic instructions that can set overflow bit // -def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "add $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; -def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "addc $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, PPC970_DGroup_Cracked; -def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "adde $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; -def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "divw $rT, $rA, $rB", IntDivW, [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "divwu $rT, $rA, $rB", IntDivW, [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, PPC970_DGroup_First, PPC970_DGroup_Cracked; -def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "mulhw $rT, $rA, $rB", IntMulHW, [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; -def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "mulhwu $rT, $rA, $rB", IntMulHWU, [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; -def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "mullw $rT, $rA, $rB", IntMulHW, [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; -def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "subf $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; -def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "subfc $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, PPC970_DGroup_Cracked; -def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB), +def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), "subfe $rT, $rA, $rB", IntGeneral, [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; -def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA), +def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), "addme $rT, $rA", IntGeneral, [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; -def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA), +def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), "addze $rT, $rA", IntGeneral, [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; -def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA), +def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), "neg $rT, $rA", IntGeneral, [(set GPRC:$rT, (ineg GPRC:$rA))]>; -def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA), +def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), "subfme $rT, $rA", IntGeneral, [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; -def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), +def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), "subfze $rT, $rA", IntGeneral, [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; } @@ -928,49 +935,49 @@ def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA), // let PPC970_Unit = 3 in { // FPU Operations. def FMADD : AForm_1<63, 29, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB))]>, Requires<[FPContractions]>; def FMADDS : AForm_1<59, 29, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB))]>, Requires<[FPContractions]>; def FMSUB : AForm_1<63, 28, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB))]>, Requires<[FPContractions]>; def FMSUBS : AForm_1<59, 28, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB))]>, Requires<[FPContractions]>; def FNMADD : AForm_1<63, 31, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB)))]>, Requires<[FPContractions]>; def FNMADDS : AForm_1<59, 31, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB)))]>, Requires<[FPContractions]>; def FNMSUB : AForm_1<63, 30, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), F8RC:$FRB)))]>, Requires<[FPContractions]>; def FNMSUBS : AForm_1<59, 30, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB)))]>, @@ -980,43 +987,43 @@ def FNMSUBS : AForm_1<59, 30, // should use an FMRSD if the input comparison value really wants to be a float) // and 4/8 byte forms for the result and operand type.. def FSELD : AForm_1<63, 23, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; def FSELS : AForm_1<63, 23, - (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), + (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; def FADD : AForm_2<63, 21, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fadd $FRT, $FRA, $FRB", FPGeneral, [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; def FADDS : AForm_2<59, 21, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fadds $FRT, $FRA, $FRB", FPGeneral, [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; def FDIV : AForm_2<63, 18, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fdiv $FRT, $FRA, $FRB", FPDivD, [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; def FDIVS : AForm_2<59, 18, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fdivs $FRT, $FRA, $FRB", FPDivS, [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; def FMUL : AForm_3<63, 25, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fmul $FRT, $FRA, $FRB", FPFused, [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; def FMULS : AForm_3<59, 25, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fmuls $FRT, $FRA, $FRB", FPGeneral, [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; def FSUB : AForm_2<63, 20, - (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), + (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "fsub $FRT, $FRA, $FRB", FPGeneral, [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; def FSUBS : AForm_2<59, 20, - (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fsubs $FRT, $FRA, $FRB", FPGeneral, [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; } @@ -1027,21 +1034,21 @@ let PPC970_Unit = 1 in { // FXU Operations. let isCommutable = 1 in { // RLWIMI can be commuted if the rotate amount is zero. def RLWIMI : MForm_2<20, - (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, + (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; } def RLWINM : MForm_2<21, - (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, []>; def RLWINMo : MForm_2<21, - (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, []>, isDOT, PPC970_DGroup_Cracked; def RLWNM : MForm_2<23, - (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), + (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, []>; } @@ -1051,7 +1058,7 @@ def RLWNM : MForm_2<23, // DWARF Pseudo Instructions // -def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file), +def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), "${:comment} .loc $file, $line, $col", [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 19780a8bf4..ee320f811b 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -248,8 +248,8 @@ void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MBB.insert(I, MI); } -const unsigned* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) - const { +const unsigned* +PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // 32-bit Darwin calling convention. static const unsigned Macho32_CalleeSavedRegs[] = { PPC::R13, PPC::R14, PPC::R15, diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 4112034aac..0a1446eb78 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -59,8 +59,8 @@ public: const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; - const TargetRegisterClass* const* getCalleeSavedRegClasses( - const MachineFunction *MF = 0) const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td index f463ab8725..9e1e159c0c 100644 --- a/lib/Target/Sparc/SparcInstrFormats.td +++ b/lib/Target/Sparc/SparcInstrFormats.td @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// -class InstSP<dag ops, string asmstr, list<dag> pattern> : Instruction { +class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32> Inst; let Namespace = "SP"; @@ -15,7 +15,8 @@ class InstSP<dag ops, string asmstr, list<dag> pattern> : Instruction { bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field - dag OperandList = ops; + dag OutOperandList = outs; + dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; } @@ -25,8 +26,8 @@ class InstSP<dag ops, string asmstr, list<dag> pattern> : Instruction { //===----------------------------------------------------------------------===// // Format 2 instructions -class F2<dag ops, string asmstr, list<dag> pattern> - : InstSP<ops, asmstr, pattern> { +class F2<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSP<outs, ins, asmstr, pattern> { bits<3> op2; bits<22> imm22; let op = 0; // op = 0 @@ -36,8 +37,8 @@ class F2<dag ops, string asmstr, list<dag> pattern> // Specific F2 classes: SparcV8 manual, page 44 // -class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> - : F2<ops, asmstr, pattern> { +class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> + : F2<outs, ins, asmstr, pattern> { bits<5> rd; let op2 = op2Val; @@ -45,8 +46,8 @@ class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> let Inst{29-25} = rd; } -class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, - list<dag> pattern> : F2<ops, asmstr, pattern> { +class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr, + list<dag> pattern> : F2<outs, ins, asmstr, pattern> { bits<4> cond; bit annul = 0; // currently unused @@ -61,8 +62,8 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, // Format #3 instruction classes in the Sparc //===----------------------------------------------------------------------===// -class F3<dag ops, string asmstr, list<dag> pattern> - : InstSP<ops, asmstr, pattern> { +class F3<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSP<outs, ins, asmstr, pattern> { bits<5> rd; bits<6> op3; bits<5> rs1; @@ -74,8 +75,8 @@ class F3<dag ops, string asmstr, list<dag> pattern> // Specific F3 classes: SparcV8 manual, page 44 // -class F3_1<bits<2> opVal, bits<6> op3val, dag ops, - string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> { +class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, + string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { bits<8> asi = 0; // asi not currently used bits<5> rs2; @@ -87,8 +88,8 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops, let Inst{4-0} = rs2; } -class F3_2<bits<2> opVal, bits<6> op3val, dag ops, - string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> { +class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, + string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { bits<13> simm13; let op = opVal; @@ -99,8 +100,8 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops, } // floating-point -class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops, - string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> { +class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, + string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { bits<5> rs2; let op = opVal; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 434e8d7472..7a32f07bc9 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -173,11 +173,11 @@ def FCC_O : FCC_VAL<29>; // Ordered /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { def rr : F3_1<2, Op3Val, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; def ri : F3_2<2, Op3Val, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; } @@ -186,10 +186,10 @@ multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { /// pattern. multiclass F3_12np<string OpcStr, bits<6> Op3Val> { def rr : F3_1<2, Op3Val, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst"), []>; def ri : F3_2<2, Op3Val, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), !strconcat(OpcStr, " $b, $c, $dst"), []>; } @@ -198,32 +198,32 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val> { //===----------------------------------------------------------------------===// // Pseudo instructions. -class Pseudo<dag ops, string asmstr, list<dag> pattern> - : InstSP<ops, asmstr, pattern>; +class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSP<outs, ins, asmstr, pattern>; -def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>, Imp<[O6],[O6]>; -def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), +def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt), "!ADJCALLSTACKUP $amt", [(callseq_end imm:$amt)]>, Imp<[O6],[O6]>; -def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), +def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins), "!IMPLICIT_DEF $dst", [(set IntRegs:$dst, (undef))]>; -def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", +def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", [(set FPRegs:$dst, (undef))]>; -def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", +def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", [(set DFPRegs:$dst, (undef))]>; // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the // fpmover pass. let Predicates = [HasNoV9] in { // Only emit these in V8 mode. - def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), + def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), "!FpMOVD $src, $dst", []>; - def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), + def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), "!FpNEGD $src, $dst", [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; - def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), + def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), "!FpABSD $src, $dst", [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; } @@ -233,32 +233,32 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode. // selection between i32/f32/f64 on ICC and FCC. let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. def SELECT_CC_Int_ICC - : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), + : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), "; SELECT_CC_Int_ICC PSEUDO!", [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, imm:$Cond))]>; def SELECT_CC_Int_FCC - : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), + : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), "; SELECT_CC_Int_FCC PSEUDO!", [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, imm:$Cond))]>; def SELECT_CC_FP_ICC - : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), + : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), "; SELECT_CC_FP_ICC PSEUDO!", [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, imm:$Cond))]>; def SELECT_CC_FP_FCC - : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), + : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), "; SELECT_CC_FP_FCC PSEUDO!", [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, imm:$Cond))]>; def SELECT_CC_DFP_ICC - : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), + : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), "; SELECT_CC_DFP_ICC PSEUDO!", [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, imm:$Cond))]>; def SELECT_CC_DFP_FCC - : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), + : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), "; SELECT_CC_DFP_FCC PSEUDO!", [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, imm:$Cond))]>; @@ -269,152 +269,152 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. // special cases of JMPL: let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in - def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; + def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; } // Section B.1 - Load Integer Instructions, p. 90 def LDSBrr : F3_1<3, 0b001001, - (ops IntRegs:$dst, MEMrr:$addr), + (outs IntRegs:$dst), (ins MEMrr:$addr), "ldsb [$addr], $dst", [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; def LDSBri : F3_2<3, 0b001001, - (ops IntRegs:$dst, MEMri:$addr), + (outs IntRegs:$dst), (ins MEMri:$addr), "ldsb [$addr], $dst", [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; def LDSHrr : F3_1<3, 0b001010, - (ops IntRegs:$dst, MEMrr:$addr), + (outs IntRegs:$dst), (ins MEMrr:$addr), "ldsh [$addr], $dst", [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; def LDSHri : F3_2<3, 0b001010, - (ops IntRegs:$dst, MEMri:$addr), + (outs IntRegs:$dst), (ins MEMri:$addr), "ldsh [$addr], $dst", [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; def LDUBrr : F3_1<3, 0b000001, - (ops IntRegs:$dst, MEMrr:$addr), + (outs IntRegs:$dst), (ins MEMrr:$addr), "ldub [$addr], $dst", [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; def LDUBri : F3_2<3, 0b000001, - (ops IntRegs:$dst, MEMri:$addr), + (outs IntRegs:$dst), (ins MEMri:$addr), "ldub [$addr], $dst", [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; def LDUHrr : F3_1<3, 0b000010, - (ops IntRegs:$dst, MEMrr:$addr), + (outs IntRegs:$dst), (ins MEMrr:$addr), "lduh [$addr], $dst", [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; def LDUHri : F3_2<3, 0b000010, - (ops IntRegs:$dst, MEMri:$addr), + (outs IntRegs:$dst), (ins MEMri:$addr), "lduh [$addr], $dst", [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; def LDrr : F3_1<3, 0b000000, - (ops IntRegs:$dst, MEMrr:$addr), + (outs IntRegs:$dst), (ins MEMrr:$addr), "ld [$addr], $dst", [(set IntRegs:$dst, (load ADDRrr:$addr))]>; def LDri : F3_2<3, 0b000000, - (ops IntRegs:$dst, MEMri:$addr), + (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set IntRegs:$dst, (load ADDRri:$addr))]>; // Section B.2 - Load Floating-point Instructions, p. 92 def LDFrr : F3_1<3, 0b100000, - (ops FPRegs:$dst, MEMrr:$addr), + (outs FPRegs:$dst), (ins MEMrr:$addr), "ld [$addr], $dst", [(set FPRegs:$dst, (load ADDRrr:$addr))]>; def LDFri : F3_2<3, 0b100000, - (ops FPRegs:$dst, MEMri:$addr), + (outs FPRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set FPRegs:$dst, (load ADDRri:$addr))]>; def LDDFrr : F3_1<3, 0b100011, - (ops DFPRegs:$dst, MEMrr:$addr), + (outs DFPRegs:$dst), (ins MEMrr:$addr), "ldd [$addr], $dst", [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; def LDDFri : F3_2<3, 0b100011, - (ops DFPRegs:$dst, MEMri:$addr), + (outs DFPRegs:$dst), (ins MEMri:$addr), "ldd [$addr], $dst", [(set DFPRegs:$dst, (load ADDRri:$addr))]>; // Section B.4 - Store Integer Instructions, p. 95 def STBrr : F3_1<3, 0b000101, - (ops MEMrr:$addr, IntRegs:$src), + (outs), (ins MEMrr:$addr, IntRegs:$src), "stb $src, [$addr]", [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; def STBri : F3_2<3, 0b000101, - (ops MEMri:$addr, IntRegs:$src), + (outs), (ins MEMri:$addr, IntRegs:$src), "stb $src, [$addr]", [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; def STHrr : F3_1<3, 0b000110, - (ops MEMrr:$addr, IntRegs:$src), + (outs), (ins MEMrr:$addr, IntRegs:$src), "sth $src, [$addr]", [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; def STHri : F3_2<3, 0b000110, - (ops MEMri:$addr, IntRegs:$src), + (outs), (ins MEMri:$addr, IntRegs:$src), "sth $src, [$addr]", [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; def STrr : F3_1<3, 0b000100, - (ops MEMrr:$addr, IntRegs:$src), + (outs), (ins MEMrr:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; def STri : F3_2<3, 0b000100, - (ops MEMri:$addr, IntRegs:$src), + (outs), (ins MEMri:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRri:$addr)]>; // Section B.5 - Store Floating-point Instructions, p. 97 def STFrr : F3_1<3, 0b100100, - (ops MEMrr:$addr, FPRegs:$src), + (outs), (ins MEMrr:$addr, FPRegs:$src), "st $src, [$addr]", [(store FPRegs:$src, ADDRrr:$addr)]>; def STFri : F3_2<3, 0b100100, - (ops MEMri:$addr, FPRegs:$src), + (outs), (ins MEMri:$addr, FPRegs:$src), "st $src, [$addr]", [(store FPRegs:$src, ADDRri:$addr)]>; def STDFrr : F3_1<3, 0b100111, - (ops MEMrr:$addr, DFPRegs:$src), + (outs), (ins MEMrr:$addr, DFPRegs:$src), "std $src, [$addr]", [(store DFPRegs:$src, ADDRrr:$addr)]>; def STDFri : F3_2<3, 0b100111, - (ops MEMri:$addr, DFPRegs:$src), + (outs), (ins MEMri:$addr, DFPRegs:$src), "std $src, [$addr]", [(store DFPRegs:$src, ADDRri:$addr)]>; // Section B.9 - SETHI Instruction, p. 104 def SETHIi: F2_1<0b100, - (ops IntRegs:$dst, i32imm:$src), + (outs IntRegs:$dst), (ins i32imm:$src), "sethi $src, $dst", [(set IntRegs:$dst, SETHIimm:$src)]>; // Section B.10 - NOP Instruction, p. 105 // (It's a special case of SETHI) let rd = 0, imm22 = 0 in - def NOP : F2_1<0b100, (ops), "nop", []>; + def NOP : F2_1<0b100, (outs), (ins), "nop", []>; // Section B.11 - Logical Instructions, p. 106 defm AND : F3_12<"and", 0b000001, and>; def ANDNrr : F3_1<2, 0b000101, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), "andn $b, $c, $dst", [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; def ANDNri : F3_2<2, 0b000101, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), "andn $b, $c, $dst", []>; defm OR : F3_12<"or", 0b000010, or>; def ORNrr : F3_1<2, 0b000110, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), "orn $b, $c, $dst", [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; def ORNri : F3_2<2, 0b000110, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), "orn $b, $c, $dst", []>; defm XOR : F3_12<"xor", 0b000011, xor>; def XNORrr : F3_1<2, 0b000111, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), "xnor $b, $c, $dst", [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; def XNORri : F3_2<2, 0b000111, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), "xnor $b, $c, $dst", []>; // Section B.12 - Shift Instructions, p. 107 @@ -427,7 +427,7 @@ defm ADD : F3_12<"add", 0b000000, add>; // "LEA" forms of add (patterns to make tblgen happy) def LEA_ADDri : F3_2<2, 0b000000, - (ops IntRegs:$dst, MEMri:$addr), + (outs IntRegs:$dst), (ins MEMri:$addr), "add ${addr:arith}, $dst", [(set IntRegs:$dst, ADDRri:$addr)]>; @@ -440,7 +440,7 @@ defm SUBX : F3_12 <"subx" , 0b001100, sube>; defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; def SUBXCCrr: F3_1<2, 0b011100, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), "subxcc $b, $c, $dst", []>; // Section B.18 - Multiply Instructions, p. 113 @@ -459,8 +459,8 @@ defm RESTORE : F3_12np<"restore", 0b111101>; // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 // conditional branch class: -class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> - : F2_2<cc, 0b010, ops, asmstr, pattern> { +class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> + : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; @@ -468,12 +468,12 @@ class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> } let isBarrier = 1 in - def BA : BranchSP<0b1000, (ops brtarget:$dst), + def BA : BranchSP<0b1000, (ins brtarget:$dst), "ba $dst", [(br bb:$dst)]>; // FIXME: the encoding for the JIT should look at the condition field. -def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc), +def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), "b$cc $dst", [(SPbricc bb:$dst, imm:$cc)]>; @@ -481,8 +481,8 @@ def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc), // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 // floating-point conditional branch class: -class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> - : F2_2<cc, 0b110, ops, asmstr, pattern> { +class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> + : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; @@ -490,7 +490,7 @@ class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> } // FIXME: the encoding for the JIT should look at the condition field. -def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc), +def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), "fb$cc $dst", [(SPbrfcc bb:$dst, imm:$cc)]>; @@ -501,7 +501,7 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1, noResults = 1, Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { - def CALL : InstSP<(ops calltarget:$dst), + def CALL : InstSP<(outs), (ins calltarget:$dst), "call $dst", []> { bits<30> disp; let op = 1; @@ -510,79 +510,79 @@ let Uses = [O0, O1, O2, O3, O4, O5], // indirect calls def JMPLrr : F3_1<2, 0b111000, - (ops MEMrr:$ptr), + (outs), (ins MEMrr:$ptr), "call $ptr", [(call ADDRrr:$ptr)]>; def JMPLri : F3_2<2, 0b111000, - (ops MEMri:$ptr), + (outs), (ins MEMri:$ptr), "call $ptr", [(call ADDRri:$ptr)]>; } // Section B.28 - Read State Register Instructions def RDY : F3_1<2, 0b101000, - (ops IntRegs:$dst), + (outs IntRegs:$dst), (ins), "rd %y, $dst", []>; // Section B.29 - Write State Register Instructions def WRYrr : F3_1<2, 0b110000, - (ops IntRegs:$b, IntRegs:$c), + (outs), (ins IntRegs:$b, IntRegs:$c), "wr $b, $c, %y", []>; def WRYri : F3_2<2, 0b110000, - (ops IntRegs:$b, i32imm:$c), + (outs), (ins IntRegs:$b, i32imm:$c), "wr $b, $c, %y", []>; // Convert Integer to Floating-point Instructions, p. 141 def FITOS : F3_3<2, 0b110100, 0b011000100, - (ops FPRegs:$dst, FPRegs:$src), + (outs FPRegs:$dst), (ins FPRegs:$src), "fitos $src, $dst", [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; def FITOD : F3_3<2, 0b110100, 0b011001000, - (ops DFPRegs:$dst, FPRegs:$src), + (outs DFPRegs:$dst), (ins FPRegs:$src), "fitod $src, $dst", [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; // Convert Floating-point to Integer Instructions, p. 142 def FSTOI : F3_3<2, 0b110100, 0b011010001, - (ops FPRegs:$dst, FPRegs:$src), + (outs FPRegs:$dst), (ins FPRegs:$src), "fstoi $src, $dst", [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; def FDTOI : F3_3<2, 0b110100, 0b011010010, - (ops FPRegs:$dst, DFPRegs:$src), + (outs FPRegs:$dst), (ins DFPRegs:$src), "fdtoi $src, $dst", [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; // Convert between Floating-point Formats Instructions, p. 143 def FSTOD : F3_3<2, 0b110100, 0b011001001, - (ops DFPRegs:$dst, FPRegs:$src), + (outs DFPRegs:$dst), (ins FPRegs:$src), "fstod $src, $dst", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; def FDTOS : F3_3<2, 0b110100, 0b011000110, - (ops FPRegs:$dst, DFPRegs:$src), + (outs FPRegs:$dst), (ins DFPRegs:$src), "fdtos $src, $dst", [(set FPRegs:$dst, (fround DFPRegs:$src))]>; // Floating-point Move Instructions, p. 144 def FMOVS : F3_3<2, 0b110100, 0b000000001, - (ops FPRegs:$dst, FPRegs:$src), + (outs FPRegs:$dst), (ins FPRegs:$src), "fmovs $src, $dst", []>; def FNEGS : F3_3<2, 0b110100, 0b000000101, - (ops FPRegs:$dst, FPRegs:$src), + (outs FPRegs:$dst), (ins FPRegs:$src), "fnegs $src, $dst", [(set FPRegs:$dst, (fneg FPRegs:$src))]>; def FABSS : F3_3<2, 0b110100, 0b000001001, - (ops FPRegs:$dst, FPRegs:$src), + (outs FPRegs:$dst), (ins FPRegs:$src), "fabss $src, $dst", [(set FPRegs:$dst, (fabs FPRegs:$src))]>; // Floating-point Square Root Instructions, p.145 def FSQRTS : F3_3<2, 0b110100, 0b000101001, - (ops FPRegs:$dst, FPRegs:$src), + (outs FPRegs:$dst), (ins FPRegs:$src), "fsqrts $src, $dst", [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; def FSQRTD : F3_3<2, 0b110100, 0b000101010, - (ops DFPRegs:$dst, DFPRegs:$src), + (outs DFPRegs:$dst), (ins DFPRegs:$src), "fsqrtd $src, $dst", [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; @@ -590,42 +590,42 @@ def FSQRTD : F3_3<2, 0b110100, 0b000101010, // Floating-point Add and Subtract Instructions, p. 146 def FADDS : F3_3<2, 0b110100, 0b001000001, - (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), + (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), "fadds $src1, $src2, $dst", [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; def FADDD : F3_3<2, 0b110100, 0b001000010, - (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), + (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), "faddd $src1, $src2, $dst", [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; def FSUBS : F3_3<2, 0b110100, 0b001000101, - (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), + (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), "fsubs $src1, $src2, $dst", [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; def FSUBD : F3_3<2, 0b110100, 0b001000110, - (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), + (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), "fsubd $src1, $src2, $dst", [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; // Floating-point Multiply and Divide Instructions, p. 147 def FMULS : F3_3<2, 0b110100, 0b001001001, - (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), + (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), "fmuls $src1, $src2, $dst", [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; def FMULD : F3_3<2, 0b110100, 0b001001010, - (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), + (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), "fmuld $src1, $src2, $dst", [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; def FSMULD : F3_3<2, 0b110100, 0b001101001, - (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), + (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), "fsmuld $src1, $src2, $dst", [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), (fextend FPRegs:$src2)))]>; def FDIVS : F3_3<2, 0b110100, 0b001001101, - (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), + (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), "fdivs $src1, $src2, $dst", [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; def FDIVD : F3_3<2, 0b110100, 0b001001110, - (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), + (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), "fdivd $src1, $src2, $dst", [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; @@ -635,11 +635,11 @@ def FDIVD : F3_3<2, 0b110100, 0b001001110, // after the instr is retired, but there is no interlock. This behavior // is modelled with a forced noop after the instruction. def FCMPS : F3_3<2, 0b110101, 0b001010001, - (ops FPRegs:$src1, FPRegs:$src2), + (outs), (ins FPRegs:$src1, FPRegs:$src2), "fcmps $src1, $src2\n\tnop", [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; def FCMPD : F3_3<2, 0b110101, 0b001010010, - (ops DFPRegs:$src1, DFPRegs:$src2), + (outs), (ins DFPRegs:$src1, DFPRegs:$src2), "fcmpd $src1, $src2\n\tnop", [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; @@ -653,44 +653,44 @@ let Predicates = [HasV9], isTwoAddress = 1 in { // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. // FIXME: Add instruction encodings for the JIT some day. def MOVICCrr - : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), + : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), "mov$cc %icc, $F, $dst", [(set IntRegs:$dst, (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; def MOVICCri - : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), + : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), "mov$cc %icc, $F, $dst", [(set IntRegs:$dst, (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; def MOVFCCrr - : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), + : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), "mov$cc %fcc0, $F, $dst", [(set IntRegs:$dst, (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; def MOVFCCri - : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), + : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), "mov$cc %fcc0, $F, $dst", [(set IntRegs:$dst, (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; def FMOVS_ICC - : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), + : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), "fmovs$cc %icc, $F, $dst", [(set FPRegs:$dst, (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; def FMOVD_ICC - : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), + : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), "fmovd$cc %icc, $F, $dst", [(set DFPRegs:$dst, (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; def FMOVS_FCC - : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), + : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), "fmovs$cc %fcc0, $F, $dst", [(set FPRegs:$dst, (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; def FMOVD_FCC - : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), + : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), "fmovd$cc %fcc0, $F, $dst", [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; @@ -700,14 +700,14 @@ let Predicates = [HasV9], isTwoAddress = 1 in { // Floating-Point Move Instructions, p. 164 of the V9 manual. let Predicates = [HasV9] in { def FMOVD : F3_3<2, 0b110100, 0b000000010, - (ops DFPRegs:$dst, DFPRegs:$src), + (outs DFPRegs:$dst), (ins DFPRegs:$src), "fmovd $src, $dst", []>; def FNEGD : F3_3<2, 0b110100, 0b000000110, - (ops DFPRegs:$dst, DFPRegs:$src), + (outs DFPRegs:$dst), (ins DFPRegs:$src), "fnegd $src, $dst", [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; def FABSD : F3_3<2, 0b110100, 0b000001010, - (ops DFPRegs:$dst, DFPRegs:$src), + (outs DFPRegs:$dst), (ins DFPRegs:$src), "fabsd $src, $dst", [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; } @@ -715,7 +715,7 @@ let Predicates = [HasV9] in { // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear // the top 32-bits before using it. To do this clearing, we use a SLLri X,0. def POPCrr : F3_1<2, 0b101110, - (ops IntRegs:$dst, IntRegs:$src), + (outs IntRegs:$dst), (ins IntRegs:$src), "popc $src, $dst", []>, Requires<[HasV9]>; def : Pat<(ctpop IntRegs:$src), (POPCrr (SLLri IntRegs:$src, 0))>; diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 48af21890f..0c0d66d753 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -151,7 +151,8 @@ class Instruction { string Name = ""; // The opcode string for this instruction string Namespace = ""; - dag OperandList; // An dag containing the MI operand list. + dag OutOperandList; // An dag containing the MI def operand list. + dag InOperandList; // An dag containing the MI use operand list. string AsmString = ""; // The .s format to print the instruction with. // Pattern - Set to the DAG pattern for this instruction, if we know of one, @@ -226,9 +227,13 @@ class Requires<list<Predicate> preds> { } /// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. This should be used like this: -/// (ops R32:$dst, R32:$src) or something similar. +/// list for an instruction. outs and ins are identical both syntatically and +/// semantically, they are used to define def operands and use operands to +/// improve readibility. This should be used like this: +/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; +def outs; +def ins; /// variable_ops definition - Mark this instruction as taking a variable number /// of operands. @@ -299,17 +304,20 @@ class InstrInfo { // Standard Instructions. def PHI : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = "PHINODE"; let Namespace = "TargetInstrInfo"; } def INLINEASM : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = ""; let Namespace = "TargetInstrInfo"; } def LABEL : Instruction { - let OperandList = (ops i32imm:$id); + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id); let AsmString = ""; let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 11aeb072c7..3ef1cde6f7 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -71,34 +71,34 @@ def fpimmneg1 : PatLeaf<(fpimm), [{ // Some 'special' instructions let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. def FP32_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP32:$src), + (outs), (ins i16mem:$dst, RFP32:$src), "#FP32_TO_INT16_IN_MEM PSEUDO!", [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; def FP32_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP32:$src), + (outs), (ins i32mem:$dst, RFP32:$src), "#FP32_TO_INT32_IN_MEM PSEUDO!", [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; def FP32_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP32:$src), + (outs), (ins i64mem:$dst, RFP32:$src), "#FP32_TO_INT64_IN_MEM PSEUDO!", [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; def FP64_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP64:$src), + (outs), (ins i16mem:$dst, RFP64:$src), "#FP64_TO_INT16_IN_MEM PSEUDO!", [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; def FP64_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP64:$src), + (outs), (ins i32mem:$dst, RFP64:$src), "#FP64_TO_INT32_IN_MEM PSEUDO!", [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; def FP64_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP64:$src), + (outs), (ins i64mem:$dst, RFP64:$src), "#FP64_TO_INT64_IN_MEM PSEUDO!", [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; } let isTerminator = 1 in let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in - def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; + def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>; // All FP Stack operations are represented with three instructions here. The // first two instructions, generated by the instruction selector, uses "RFP32" @@ -120,81 +120,82 @@ let isTerminator = 1 in // encoding and asm printing info). // FPI - Floating Point Instruction template. -class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {} +class FPI<bits<8> o, Format F, dag outs, dag ins, string asm> + : I<o, F, outs, ins, asm, []> {} // FpI_ - Floating Point Psuedo Instruction template. Not Predicated. -class FpI_<dag ops, FPFormat fp, list<dag> pattern> - : X86Inst<0, Pseudo, NoImm, ops, ""> { +class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern> + : X86Inst<0, Pseudo, NoImm, outs, ins, ""> { let FPForm = fp; let FPFormBits = FPForm.Value; let Pattern = pattern; } // Random Pseudo Instructions. -def FpGETRESULT32 : FpI_<(ops RFP32:$dst), SpecialFP, +def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0) -def FpGETRESULT64 : FpI_<(ops RFP64:$dst), SpecialFP, +def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0) let noResults = 1 in { - def FpSETRESULT32 : FpI_<(ops RFP32:$src), SpecialFP, + def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR - def FpSETRESULT64 : FpI_<(ops RFP64:$src), SpecialFP, + def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR } // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack. -class FpI<dag ops, FPFormat fp, list<dag> pattern> : - FpI_<ops, fp, pattern>, Requires<[FPStack]>; +class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> : + FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>; // Register copies. Just copies, the 64->32 version does not truncate. -def MOV_Fp3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; -def MOV_Fp3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; -def MOV_Fp6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; -def MOV_Fp6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; +def MOV_Fp3232 : FpI<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; +def MOV_Fp3264 : FpI<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; +def MOV_Fp6432 : FpI<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; +def MOV_Fp6464 : FpI<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>; // Factoring for arithmetic. multiclass FPBinary_rr<SDNode OpNode> { // Register op register -> register // These are separated out because they have no reversed form. -def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, +def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; -def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, +def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; } // The FopST0 series are not included here because of the irregularities // in where the 'r' goes in assembly output. multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { // ST(0) = ST(0) + [mem] -def _Fp32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, +def _Fp32m : FpI<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; -def _Fp64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, +def _Fp64m : FpI<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; -def _Fp64m32: FpI<(ops RFP64:$dst, RFP64:$src1, f32mem:$src2), OneArgFPRW, +def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (extloadf32 addr:$src2)))]>; -def _F32m : FPI<0xD8, fp, (ops f32mem:$src), +def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), !strconcat("f", !strconcat(asmstring, "{s} $src"))>; -def _F64m : FPI<0xDC, fp, (ops f64mem:$src), +def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), !strconcat("f", !strconcat(asmstring, "{l} $src"))>; // ST(0) = ST(0) + [memint] -def _FpI16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, +def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src1, (X86fild addr:$src2, i16)))]>; -def _FpI32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, +def _FpI32m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src1, (X86fild addr:$src2, i32)))]>; -def _FpI16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, +def _FpI16m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (X86fild addr:$src2, i16)))]>; -def _FpI32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, +def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (X86fild addr:$src2, i32)))]>; -def _FI16m : FPI<0xDE, fp, (ops i16mem:$src), +def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), !strconcat("fi", !strconcat(asmstring, "{s} $src"))>; -def _FI32m : FPI<0xDA, fp, (ops i32mem:$src), +def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), !strconcat("fi", !strconcat(asmstring, "{l} $src"))>; } @@ -210,11 +211,11 @@ defm DIV : FPBinary<fdiv, MRM6m, "div">; defm DIVR: FPBinary<fdiv, MRM7m, "divr">; class FPST0rInst<bits<8> o, string asm> - : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8; + : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8; class FPrST0Inst<bits<8> o, string asm> - : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC; + : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC; class FPrST0PInst<bits<8> o, string asm> - : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE; + : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE; // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, @@ -240,11 +241,11 @@ def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; // Unary operations. multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> { -def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, +def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src))]>; -def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, +def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src))]>; -def _F : FPI<opcode, RawFrm, (ops), asmstring>, D9; +def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9; } defm CHS : FPUnary<fneg, 0xE0, "fchs">; @@ -253,18 +254,18 @@ defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">; defm SIN : FPUnary<fsin, 0xFE, "fsin">; defm COS : FPUnary<fcos, 0xFF, "fcos">; -def TST_Fp32 : FpI<(ops RFP32:$src), OneArgFP, +def TST_Fp32 : FpI<(outs), (ins RFP32:$src), OneArgFP, []>; -def TST_Fp64 : FpI<(ops RFP64:$src), OneArgFP, +def TST_Fp64 : FpI<(outs), (ins RFP64:$src), OneArgFP, []>; -def TST_F : FPI<0xE4, RawFrm, (ops), "ftst">, D9; +def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; // Floating point cmovs. multiclass FPCMov<PatLeaf cc> { - def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, cc))]>; - def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, cc))]>; } @@ -280,154 +281,154 @@ defm CMOVNP : FPCMov<X86_COND_NP>; } // These are not factored because there's no clean way to pass DA/DB. -def CMOVB_F : FPI<0xC0, AddRegFrm, (ops RST:$op), +def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), "fcmovb {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVBE_F : FPI<0xD0, AddRegFrm, (ops RST:$op), +def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVE_F : FPI<0xC8, AddRegFrm, (ops RST:$op), +def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), "fcmove {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVP_F : FPI<0xD8, AddRegFrm, (ops RST:$op), +def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), "fcmovu {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVNB_F : FPI<0xC0, AddRegFrm, (ops RST:$op), +def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB; -def CMOVNBE_F: FPI<0xD0, AddRegFrm, (ops RST:$op), +def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB; -def CMOVNE_F : FPI<0xC8, AddRegFrm, (ops RST:$op), +def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), "fcmovne {$op, %st(0)|%ST(0), $op}">, DB; -def CMOVNP_F : FPI<0xD8, AddRegFrm, (ops RST:$op), +def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -def LD_Fp32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, +def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, [(set RFP32:$dst, (loadf32 addr:$src))]>; -def LD_Fp64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, +def LD_Fp64m : FpI<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, [(set RFP64:$dst, (loadf64 addr:$src))]>; -def ILD_Fp16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, +def ILD_Fp16m32: FpI<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i16))]>; -def ILD_Fp32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, +def ILD_Fp32m32: FpI<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i32))]>; -def ILD_Fp64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, +def ILD_Fp64m32: FpI<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i64))]>; -def ILD_Fp16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, +def ILD_Fp16m64: FpI<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i16))]>; -def ILD_Fp32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, +def ILD_Fp32m64: FpI<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i32))]>; -def ILD_Fp64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, +def ILD_Fp64m64: FpI<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i64))]>; -def ST_Fp32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, +def ST_Fp32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, [(store RFP32:$src, addr:$op)]>; -def ST_Fp64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, +def ST_Fp64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, [(truncstoref32 RFP64:$src, addr:$op)]>; -def ST_Fp64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, +def ST_Fp64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, [(store RFP64:$src, addr:$op)]>; -def ST_FpP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>; -def ST_FpP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>; -def ST_FpP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>; -def IST_Fp16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>; -def IST_Fp32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>; -def IST_Fp64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>; -def IST_Fp16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>; -def IST_Fp32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>; -def IST_Fp64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>; - -def LD_F32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; -def LD_F64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; -def ILD_F16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">; -def ILD_F32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">; -def ILD_F64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">; -def ST_F32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">; -def ST_F64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">; -def ST_FP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">; -def ST_FP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">; -def IST_F16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">; -def IST_F32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">; -def IST_FP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">; -def IST_FP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">; -def IST_FP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; +def ST_FpP32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; +def ST_FpP64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp16m32 : FpI<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp32m32 : FpI<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp64m32 : FpI<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; + +def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s} $src">; +def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l} $src">; +def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s} $src">; +def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l} $src">; +def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll} $src">; +def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s} $dst">; +def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l} $dst">; +def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s} $dst">; +def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l} $dst">; +def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s} $dst">; +def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l} $dst">; +def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s} $dst">; +def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l} $dst">; +def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll} $dst">; // FISTTP requires SSE3 even though it's a FPStack op. -def ISTT_Fp16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_FP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">; -def ISTT_FP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">; -def ISTT_FP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">; +def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s} $dst">; +def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l} $dst">; +def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll} $dst">; // FP Stack manipulation instructions. -def LD_Frr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9; -def ST_Frr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD; -def ST_FPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; -def XCH_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; +def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld $op">, D9; +def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst $op">, DD; +def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp $op">, DD; +def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch $op">, D9; // Floating point constant loads. let isReMaterializable = 1 in { -def LD_Fp032 : FpI<(ops RFP32:$dst), ZeroArgFP, +def LD_Fp032 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP, [(set RFP32:$dst, fpimm0)]>; -def LD_Fp132 : FpI<(ops RFP32:$dst), ZeroArgFP, +def LD_Fp132 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP, [(set RFP32:$dst, fpimm1)]>; -def LD_Fp064 : FpI<(ops RFP64:$dst), ZeroArgFP, +def LD_Fp064 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP, [(set RFP64:$dst, fpimm0)]>; -def LD_Fp164 : FpI<(ops RFP64:$dst), ZeroArgFP, +def LD_Fp164 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP, [(set RFP64:$dst, fpimm1)]>; } -def LD_F0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; -def LD_F1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; +def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9; +def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9; // Floating point compares. -def UCOM_Fpr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, +def UCOM_Fpr32 : FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def UCOM_FpIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, +def UCOM_FpIr32: FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i) -def UCOM_Fpr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, +def UCOM_Fpr64 : FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def UCOM_FpIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, +def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i) def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) - (ops RST:$reg), + (outs), (ins RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>; def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop - (ops RST:$reg), + (outs), (ins RST:$reg), "fucomp $reg">, DD, Imp<[ST0],[]>; def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop - (ops), + (outs), (ins), "fucompp">, DA, Imp<[ST0],[]>; def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) - (ops RST:$reg), + (outs), (ins RST:$reg), "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop - (ops RST:$reg), + (outs), (ins RST:$reg), "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; // Floating point flag ops. def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags - (ops), "fnstsw", []>, DF, Imp<[],[AX]>; + (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>; def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world - (ops i16mem:$dst), "fnstcw $dst", []>; + (outs), (ins i16mem:$dst), "fnstcw $dst", []>; def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] - (ops i16mem:$dst), "fldcw $dst", []>; + (outs), (ins i16mem:$dst), "fldcw $dst", []>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index b24f644207..8522d61dc1 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -220,7 +220,8 @@ def CondMovFP : FPFormat<6>; def SpecialFP : FPFormat<7>; -class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> +class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, + string AsmStr> : Instruction { let Namespace = "X86"; @@ -230,7 +231,8 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> ImmType ImmT = i; bits<3> ImmTypeBits = ImmT.Value; - dag OperandList = ops; + dag OutOperandList = outs; + dag InOperandList = ins; string AsmString = AsmStr; // @@ -335,23 +337,23 @@ def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; // Instruction templates... // -class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> - : X86Inst<o, f, NoImm, ops, asm> { +class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> + : X86Inst<o, f, NoImm, outs, ins, asm> { let Pattern = pattern; let CodeSize = 3; } -class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> - : X86Inst<o, f, Imm8 , ops, asm> { +class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> + : X86Inst<o, f, Imm8 , outs, ins, asm> { let Pattern = pattern; let CodeSize = 3; } -class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> - : X86Inst<o, f, Imm16, ops, asm> { +class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> + : X86Inst<o, f, Imm16, outs, ins, asm> { let Pattern = pattern; let CodeSize = 3; } -class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> - : X86Inst<o, f, Imm32, ops, asm> { +class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> + : X86Inst<o, f, Imm32, outs, ins, asm> { let Pattern = pattern; let CodeSize = 3; } @@ -363,33 +365,35 @@ class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into // a stack adjustment and the codegen must know that they may modify the stack // pointer before prolog-epilog rewriting occurs. -def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", +def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN", [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>; -def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), +def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), "#ADJCALLSTACKUP", [(X86callseq_end imm:$amt1, imm:$amt2)]>, Imp<[ESP],[ESP]>; -def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; -def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; -def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst), +def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops), + "#IMPLICIT_USE", []>; +def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins), + "#IMPLICIT_DEF", []>; +def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins), "#IMPLICIT_DEF $dst", [(set GR8:$dst, (undef))]>; -def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst), +def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins), "#IMPLICIT_DEF $dst", [(set GR16:$dst, (undef))]>; -def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst), +def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins), "#IMPLICIT_DEF $dst", [(set GR32:$dst, (undef))]>; // Nop -def NOOP : I<0x90, RawFrm, (ops), "nop", []>; +def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; // Truncate -def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src), +def TRUNC_32_to8 : I<0x88, MRMDestReg, (outs GR8:$dst), (ins GR32_:$src), "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>; -def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src), +def TRUNC_16_to8 : I<0x88, MRMDestReg, (outs GR8:$dst), (ins GR16_:$src), "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>; -def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src), +def TRUNC_32to16 : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR32:$src), "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}", [(set GR16:$dst, (trunc GR32:$src))]>; @@ -400,61 +404,61 @@ def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src), // Return instructions. let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1, noResults = 1 in { - def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>; - def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", + def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>; + def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret $amt", [(X86retflag imm:$amt)]>; } // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1, noResults = 1 in - class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : - I<opcode, RawFrm, ops, asm, pattern>; + class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> : + I<opcode, RawFrm, (outs), ins, asm, pattern>; // Indirect branches let isBranch = 1, isBarrier = 1 in - def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; + def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in { - def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst", + def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l} {*}$dst", [(brind GR32:$dst)]>; - def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst", + def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l} {*}$dst", [(brind (loadi32 addr:$dst))]>; } // Conditional branches -def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", +def JE : IBr<0x84, (ins brtarget:$dst), "je $dst", [(X86brcond bb:$dst, X86_COND_E)]>, TB; -def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", +def JNE : IBr<0x85, (ins brtarget:$dst), "jne $dst", [(X86brcond bb:$dst, X86_COND_NE)]>, TB; -def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", +def JL : IBr<0x8C, (ins brtarget:$dst), "jl $dst", [(X86brcond bb:$dst, X86_COND_L)]>, TB; -def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", +def JLE : IBr<0x8E, (ins brtarget:$dst), "jle $dst", [(X86brcond bb:$dst, X86_COND_LE)]>, TB; -def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", +def JG : IBr<0x8F, (ins brtarget:$dst), "jg $dst", [(X86brcond bb:$dst, X86_COND_G)]>, TB; -def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", +def JGE : IBr<0x8D, (ins brtarget:$dst), "jge $dst", [(X86brcond bb:$dst, X86_COND_GE)]>, TB; -def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst", +def JB : IBr<0x82, (ins brtarget:$dst), "jb $dst", [(X86brcond bb:$dst, X86_COND_B)]>, TB; -def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", +def JBE : IBr<0x86, (ins brtarget:$dst), "jbe $dst", [(X86brcond bb:$dst, X86_COND_BE)]>, TB; -def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", +def JA : IBr<0x87, (ins brtarget:$dst), "ja $dst", [(X86brcond bb:$dst, X86_COND_A)]>, TB; -def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", +def JAE : IBr<0x83, (ins brtarget:$dst), "jae $dst", [(X86brcond bb:$dst, X86_COND_AE)]>, TB; -def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", +def JS : IBr<0x88, (ins brtarget:$dst), "js $dst", [(X86brcond bb:$dst, X86_COND_S)]>, TB; -def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", +def JNS : IBr<0x89, (ins brtarget:$dst), "jns $dst", [(X86brcond bb:$dst, X86_COND_NS)]>, TB; -def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", +def JP : IBr<0x8A, (ins brtarget:$dst), "jp $dst", [(X86brcond bb:$dst, X86_COND_P)]>, TB; -def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", +def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp $dst", [(X86brcond bb:$dst, X86_COND_NP)]>, TB; -def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst", +def JO : IBr<0x80, (ins brtarget:$dst), "jo $dst", [(X86brcond bb:$dst, X86_COND_O)]>, TB; -def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst", +def JNO : IBr<0x81, (ins brtarget:$dst), "jno $dst", [(X86brcond bb:$dst, X86_COND_NO)]>, TB; //===----------------------------------------------------------------------===// @@ -465,150 +469,151 @@ let isCall = 1, noResults = 1 in let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { - def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops), + def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops), "call ${dst:call}", []>; - def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), + def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), "call {*}$dst", [(X86call GR32:$dst)]>; - def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops), + def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), "call {*}$dst", []>; } // Tail call stuff. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in - def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL", + def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp ${dst:call} # TAIL CALL", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in - def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL", + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp {*}$dst # TAIL CALL", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in - def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), + def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp {*}$dst # TAIL CALL", []>; //===----------------------------------------------------------------------===// // Miscellaneous Instructions... // def LEAVE : I<0xC9, RawFrm, - (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; + (outs), (ins), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; def POP32r : I<0x58, AddRegFrm, - (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; + (outs GR32:$reg), (ins), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; def PUSH32r : I<0x50, AddRegFrm, - (ops GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>; + (outs), (ins GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>; -def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label), +def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label), "call $label", []>; let isTwoAddress = 1 in // GR32 = bswap GR32 def BSWAP32r : I<0xC8, AddRegFrm, - (ops GR32:$dst, GR32:$src), + (outs GR32:$dst), (ins GR32:$src), "bswap{l} $dst", [(set GR32:$dst, (bswap GR32:$src))]>, TB; +// FIXME: Model xchg* as two address instructions? def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8 - (ops GR8:$src1, GR8:$src2), + (outs), (ins GR8:$src1, GR8:$src2), "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16 - (ops GR16:$src1, GR16:$src2), + (outs), (ins GR16:$src1, GR16:$src2), "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32 - (ops GR32:$src1, GR32:$src2), + (outs), (ins GR32:$src1, GR32:$src2), "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def XCHG8mr : I<0x86, MRMDestMem, - (ops i8mem:$src1, GR8:$src2), + (outs), (ins i8mem:$src1, GR8:$src2), "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16mr : I<0x87, MRMDestMem, - (ops i16mem:$src1, GR16:$src2), + (outs), (ins i16mem:$src1, GR16:$src2), "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32mr : I<0x87, MRMDestMem, - (ops i32mem:$src1, GR32:$src2), + (outs), (ins i32mem:$src1, GR32:$src2), "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def XCHG8rm : I<0x86, MRMSrcMem, - (ops GR8:$src1, i8mem:$src2), + (outs), (ins GR8:$src1, i8mem:$src2), "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16rm : I<0x87, MRMSrcMem, - (ops GR16:$src1, i16mem:$src2), + (outs), (ins GR16:$src1, i16mem:$src2), "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32rm : I<0x87, MRMSrcMem, - (ops GR32:$src1, i32mem:$src2), + (outs), (ins GR32:$src1, i32mem:$src2), "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def LEA16r : I<0x8D, MRMSrcMem, - (ops GR16:$dst, i32mem:$src), + (outs GR16:$dst), (ins i32mem:$src), "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; def LEA32r : I<0x8D, MRMSrcMem, - (ops GR32:$dst, lea32mem:$src), + (outs GR32:$dst), (ins lea32mem:$src), "lea{l} {$src|$dst}, {$dst|$src}", [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; -def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", +def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", [(X86rep_movs i8)]>, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; -def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", +def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", [(X86rep_movs i16)]>, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; -def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}", +def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", [(X86rep_movs i32)]>, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; -def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", +def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", [(X86rep_stos i8)]>, Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; -def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", +def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", [(X86rep_stos i16)]>, Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; -def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", +def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", [(X86rep_stos i32)]>, Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; -def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>, +def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB, Imp<[],[RAX,RDX]>; //===----------------------------------------------------------------------===// // Input/Output Instructions... // -def IN8rr : I<0xEC, RawFrm, (ops), +def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b} {%dx, %al|%AL, %DX}", []>, Imp<[DX], [AL]>; -def IN16rr : I<0xED, RawFrm, (ops), +def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w} {%dx, %ax|%AX, %DX}", []>, Imp<[DX], [AX]>, OpSize; -def IN32rr : I<0xED, RawFrm, (ops), +def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>; -def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port), +def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port), "in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>; -def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), +def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), "in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize; -def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), +def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>; -def OUT8rr : I<0xEE, RawFrm, (ops), +def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b} {%al, %dx|%DX, %AL}", []>, Imp<[DX, AL], []>; -def OUT16rr : I<0xEF, RawFrm, (ops), +def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w} {%ax, %dx|%DX, %AX}", []>, Imp<[DX, AX], []>, OpSize; -def OUT32rr : I<0xEF, RawFrm, (ops), +def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l} {%eax, %dx|%DX, %EAX}", []>, Imp<[DX, EAX], []>; -def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), +def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port), "out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>; -def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), +def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), "out{w} {%ax, $port|$port, %AX}", []>, Imp<[AX], []>, OpSize; -def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), +def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), "out{l} {%eax, $port|$port, %EAX}", []>, Imp<[EAX], []>; @@ -616,50 +621,50 @@ def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src), +def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), "mov{b} {$src, $dst|$dst, $src}", []>; -def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src), +def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src), +def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), "mov{l} {$src, $dst|$dst, $src}", []>; let isReMaterializable = 1 in { -def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src), +def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, imm:$src)]>; -def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src), +def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), "mov{w} {$src, $dst|$dst, $src}", [(set GR16:$dst, imm:$src)]>, OpSize; -def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src), +def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, imm:$src)]>; } -def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), +def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(store (i8 imm:$src), addr:$dst)]>; -def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), +def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), "mov{w} {$src, $dst|$dst, $src}", [(store (i16 imm:$src), addr:$dst)]>, OpSize; -def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), +def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", [(store (i32 imm:$src), addr:$dst)]>; -def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), +def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; -def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), +def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", [(set GR16:$dst, (load addr:$src))]>, OpSize; -def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), +def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, (load addr:$src))]>; -def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src), +def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b} {$src, $dst|$dst, $src}", [(store GR8:$src, addr:$dst)]>; -def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src), +def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), "mov{w} {$src, $dst|$dst, $src}", [(store GR16:$src, addr:$dst)]>, OpSize; -def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src), +def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "mov{l} {$src, $dst|$dst, $src}", [(store GR32:$src, addr:$dst)]>; @@ -668,70 +673,70 @@ def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src), // // Extra precision multiplication -def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src", +def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b} $src", // FIXME: Used for 8-bit mul, ignore result upper 8 bits. // This probably ought to be moved to a def : Pat<> if the // syntax can be accepted. [(set AL, (mul AL, GR8:$src))]>, Imp<[AL],[AX]>; // AL,AH = AL*GR8 -def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>, +def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w} $src", []>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 -def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>, +def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 -def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), +def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), "mul{b} $src", // FIXME: Used for 8-bit mul, ignore result upper 8 bits. // This probably ought to be moved to a def : Pat<> if the // syntax can be accepted. [(set AL, (mul AL, (loadi8 addr:$src)))]>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] -def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), +def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), "mul{w} $src", []>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] -def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), +def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] -def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>, +def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*GR8 -def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>, +def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w} $src", []>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 -def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>, +def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l} $src", []>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 -def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), +def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] -def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), +def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), "imul{w} $src", []>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] -def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), +def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), "imul{l} $src", []>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] // unsigned division/remainder -def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH +def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH "div{b} $src", []>, Imp<[AX],[AX]>; -def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX +def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; -def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX +def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; -def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH +def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH "div{b} $src", []>, Imp<[AX],[AX]>; -def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX +def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; -def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX +def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; // Signed division/remainder. -def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH +def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH "idiv{b} $src", []>, Imp<[AX],[AX]>; -def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX +def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; -def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX +def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; -def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH +def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH "idiv{b} $src", []>, Imp<[AX],[AX]>; -def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX +def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; -def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX +def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; @@ -742,350 +747,350 @@ let isTwoAddress = 1 in { // Conditional moves def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovb {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_B))]>, TB, OpSize; def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovb {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_B))]>, TB, OpSize; def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovb {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_B))]>, TB; def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovb {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_B))]>, TB; def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovae {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_AE))]>, TB, OpSize; def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovae {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_AE))]>, TB, OpSize; def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovae {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_AE))]>, TB; def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovae {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_AE))]>, TB; def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmove {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_E))]>, TB, OpSize; def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmove {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_E))]>, TB, OpSize; def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmove {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_E))]>, TB; def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmove {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_E))]>, TB; def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovne {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_NE))]>, TB, OpSize; def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovne {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_NE))]>, TB, OpSize; def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovne {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_NE))]>, TB; def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovne {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_NE))]>, TB; def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovbe {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_BE))]>, TB, OpSize; def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovbe {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_BE))]>, TB, OpSize; def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovbe {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_BE))]>, TB; def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovbe {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_BE))]>, TB; def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmova {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_A))]>, TB, OpSize; def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmova {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_A))]>, TB, OpSize; def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmova {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_A))]>, TB; def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmova {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_A))]>, TB; def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovl {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_L))]>, TB, OpSize; def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovl {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_L))]>, TB, OpSize; def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovl {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_L))]>, TB; def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovl {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_L))]>, TB; def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovge {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_GE))]>, TB, OpSize; def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovge {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_GE))]>, TB, OpSize; def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovge {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_GE))]>, TB; def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovge {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_GE))]>, TB; def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovle {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_LE))]>, TB, OpSize; def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovle {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_LE))]>, TB, OpSize; def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovle {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_LE))]>, TB; def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovle {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_LE))]>, TB; def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovg {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_G))]>, TB, OpSize; def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovg {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_G))]>, TB, OpSize; def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovg {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_G))]>, TB; def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovg {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_G))]>, TB; def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovs {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_S))]>, TB, OpSize; def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovs {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_S))]>, TB, OpSize; def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovs {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_S))]>, TB; def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovs {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_S))]>, TB; def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovns {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_NS))]>, TB, OpSize; def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovns {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_NS))]>, TB, OpSize; def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovns {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_NS))]>, TB; def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovns {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_NS))]>, TB; def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovp {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_P))]>, TB, OpSize; def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovp {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_P))]>, TB, OpSize; def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovp {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_P))]>, TB; def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovp {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_P))]>, TB; def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "cmovnp {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_NP))]>, TB, OpSize; def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "cmovnp {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_NP))]>, TB, OpSize; def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "cmovnp {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_NP))]>, TB; def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "cmovnp {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_NP))]>, @@ -1094,230 +1099,230 @@ def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] // unary instructions let CodeSize = 2 in { -def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst", +def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b} $dst", [(set GR8:$dst, (ineg GR8:$src))]>; -def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst", +def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w} $dst", [(set GR16:$dst, (ineg GR16:$src))]>, OpSize; -def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst", +def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l} $dst", [(set GR32:$dst, (ineg GR32:$src))]>; let isTwoAddress = 0 in { - def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", + def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b} $dst", [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; - def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", + def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w} $dst", [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; - def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", + def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l} $dst", [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; } -def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst", +def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b} $dst", [(set GR8:$dst, (not GR8:$src))]>; -def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst", +def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w} $dst", [(set GR16:$dst, (not GR16:$src))]>, OpSize; -def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst", +def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l} $dst", [(set GR32:$dst, (not GR32:$src))]>; let isTwoAddress = 0 in { - def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", + def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b} $dst", [(store (not (loadi8 addr:$dst)), addr:$dst)]>; - def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", + def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w} $dst", [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; - def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", + def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l} $dst", [(store (not (loadi32 addr:$dst)), addr:$dst)]>; } } // CodeSize // TODO: inc/dec is slow for P4, but fast for Pentium-M. let CodeSize = 2 in -def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", +def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b} $dst", [(set GR8:$dst, (add GR8:$src, 1))]>; let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. -def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst", +def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w} $dst", [(set GR16:$dst, (add GR16:$src, 1))]>, OpSize, Requires<[In32BitMode]>; -def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst", +def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l} $dst", [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>; } let isTwoAddress = 0, CodeSize = 2 in { - def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", + def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b} $dst", [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; - def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", + def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w} $dst", [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize; - def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", + def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l} $dst", [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; } let CodeSize = 2 in -def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst", +def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b} $dst", [(set GR8:$dst, (add GR8:$src, -1))]>; let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. -def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst", +def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w} $dst", [(set GR16:$dst, (add GR16:$src, -1))]>, OpSize, Requires<[In32BitMode]>; -def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst", +def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l} $dst", [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>; } let isTwoAddress = 0, CodeSize = 2 in { - def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", + def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b} $dst", [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; - def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", + def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w} $dst", [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize; - def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", + def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l} $dst", [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>; } // Logical operators... let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y def AND8rr : I<0x20, MRMDestReg, - (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), + (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), "and{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>; def AND16rr : I<0x21, MRMDestReg, - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "and{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize; def AND32rr : I<0x21, MRMDestReg, - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "and{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; } def AND8rm : I<0x22, MRMSrcMem, - (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), + (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), "and{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>; def AND16rm : I<0x23, MRMSrcMem, - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "and{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize; def AND32rm : I<0x23, MRMSrcMem, - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "and{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>; def AND8ri : Ii8<0x80, MRM4r, - (ops GR8 :$dst, GR8 :$src1, i8imm :$src2), + (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), "and{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>; def AND16ri : Ii16<0x81, MRM4r, - (ops GR16:$dst, GR16:$src1, i16imm:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "and{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize; def AND32ri : Ii32<0x81, MRM4r, - (ops GR32:$dst, GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "and{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; def AND16ri8 : Ii8<0x83, MRM4r, - (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "and{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>, OpSize; def AND32ri8 : Ii8<0x83, MRM4r, - (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "and{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { def AND8mr : I<0x20, MRMDestMem, - (ops i8mem :$dst, GR8 :$src), + (outs), (ins i8mem :$dst, GR8 :$src), "and{b} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>; def AND16mr : I<0x21, MRMDestMem, - (ops i16mem:$dst, GR16:$src), + (outs), (ins i16mem:$dst, GR16:$src), "and{w} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; def AND32mr : I<0x21, MRMDestMem, - (ops i32mem:$dst, GR32:$src), + (outs), (ins i32mem:$dst, GR32:$src), "and{l} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>; def AND8mi : Ii8<0x80, MRM4m, - (ops i8mem :$dst, i8imm :$src), + (outs), (ins i8mem :$dst, i8imm :$src), "and{b} {$src, $dst|$dst, $src}", [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; def AND16mi : Ii16<0x81, MRM4m, - (ops i16mem:$dst, i16imm:$src), + (outs), (ins i16mem:$dst, i16imm:$src), "and{w} {$src, $dst|$dst, $src}", [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, OpSize; def AND32mi : Ii32<0x81, MRM4m, - (ops i32mem:$dst, i32imm:$src), + (outs), (ins i32mem:$dst, i32imm:$src), "and{l} {$src, $dst|$dst, $src}", [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; def AND16mi8 : Ii8<0x83, MRM4m, - (ops i16mem:$dst, i16i8imm :$src), + (outs), (ins i16mem:$dst, i16i8imm :$src), "and{w} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, OpSize; def AND32mi8 : Ii8<0x83, MRM4m, - (ops i32mem:$dst, i32i8imm :$src), + (outs), (ins i32mem:$dst, i32i8imm :$src), "and{l} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; } let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y -def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), +def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), "or{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>; -def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), +def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "or{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize; -def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "or{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; } -def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), +def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), "or{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>; -def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2), +def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "or{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize; -def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2), +def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "or{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>; -def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), +def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), "or{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>; -def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), +def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "or{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize; -def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), +def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "or{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; -def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), +def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "or{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize; -def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), +def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "or{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src), + def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), "or{b} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; - def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src), + def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), "or{w} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; - def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src), + def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "or{l} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>; - def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), + def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), "or{b} {$src, $dst|$dst, $src}", [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; - def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), + def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), "or{w} {$src, $dst|$dst, $src}", [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, OpSize; - def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), + def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), "or{l} {$src, $dst|$dst, $src}", [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; - def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src), + def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), "or{w} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, OpSize; - def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src), + def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), "or{l} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; } @@ -1325,429 +1330,429 @@ let isTwoAddress = 0 in { let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y def XOR8rr : I<0x30, MRMDestReg, - (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), + (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), "xor{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>; def XOR16rr : I<0x31, MRMDestReg, - (ops GR16:$dst, GR16:$src1, GR16:$src2), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "xor{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize; def XOR32rr : I<0x31, MRMDestReg, - (ops GR32:$dst, GR32:$src1, GR32:$src2), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "xor{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; } def XOR8rm : I<0x32, MRMSrcMem , - (ops GR8 :$dst, GR8:$src1, i8mem :$src2), + (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), "xor{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>; def XOR16rm : I<0x33, MRMSrcMem , - (ops GR16:$dst, GR16:$src1, i16mem:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "xor{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize; def XOR32rm : I<0x33, MRMSrcMem , - (ops GR32:$dst, GR32:$src1, i32mem:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "xor{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>; def XOR8ri : Ii8<0x80, MRM6r, - (ops GR8:$dst, GR8:$src1, i8imm:$src2), + (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "xor{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>; def XOR16ri : Ii16<0x81, MRM6r, - (ops GR16:$dst, GR16:$src1, i16imm:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "xor{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize; def XOR32ri : Ii32<0x81, MRM6r, - (ops GR32:$dst, GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "xor{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; def XOR16ri8 : Ii8<0x83, MRM6r, - (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "xor{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>, OpSize; def XOR32ri8 : Ii8<0x83, MRM6r, - (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "xor{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { def XOR8mr : I<0x30, MRMDestMem, - (ops i8mem :$dst, GR8 :$src), + (outs), (ins i8mem :$dst, GR8 :$src), "xor{b} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>; def XOR16mr : I<0x31, MRMDestMem, - (ops i16mem:$dst, GR16:$src), + (outs), (ins i16mem:$dst, GR16:$src), "xor{w} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; def XOR32mr : I<0x31, MRMDestMem, - (ops i32mem:$dst, GR32:$src), + (outs), (ins i32mem:$dst, GR32:$src), "xor{l} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>; def XOR8mi : Ii8<0x80, MRM6m, - (ops i8mem :$dst, i8imm :$src), + (outs), (ins i8mem :$dst, i8imm :$src), "xor{b} {$src, $dst|$dst, $src}", [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; def XOR16mi : Ii16<0x81, MRM6m, - (ops i16mem:$dst, i16imm:$src), + (outs), (ins i16mem:$dst, i16imm:$src), "xor{w} {$src, $dst|$dst, $src}", [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, OpSize; def XOR32mi : Ii32<0x81, MRM6m, - (ops i32mem:$dst, i32imm:$src), + (outs), (ins i32mem:$dst, i32imm:$src), "xor{l} {$src, $dst|$dst, $src}", [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; def XOR16mi8 : Ii8<0x83, MRM6m, - (ops i16mem:$dst, i16i8imm :$src), + (outs), (ins i16mem:$dst, i16i8imm :$src), "xor{w} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, OpSize; def XOR32mi8 : Ii8<0x83, MRM6m, - (ops i32mem:$dst, i32i8imm :$src), + (outs), (ins i32mem:$dst, i32i8imm :$src), "xor{l} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; } // Shift instructions -def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src), +def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), "shl{b} {%cl, $dst|$dst, %CL}", [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>; -def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src), +def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), "shl{w} {%cl, $dst|$dst, %CL}", [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src), +def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), "shl{l} {%cl, $dst|$dst, %CL}", [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>; -def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), +def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), "shl{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), +def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), "shl{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; -def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), +def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), "shl{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; } // Shift left by one. Not used because (add x, x) is slightly cheaper. -def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1), +def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), "shl{b} $dst", []>; -def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1), +def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), "shl{w} $dst", []>, OpSize; -def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1), +def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), "shl{l} $dst", []>; let isTwoAddress = 0 in { - def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), + def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), "shl{b} {%cl, $dst|$dst, %CL}", [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), + def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), "shl{w} {%cl, $dst|$dst, %CL}", [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>, OpSize; - def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), + def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), "shl{l} {%cl, $dst|$dst, %CL}", [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), + def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), "shl{b} {$src, $dst|$dst, $src}", [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; - def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), + def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), "shl{w} {$src, $dst|$dst, $src}", [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, OpSize; - def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), + def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), "shl{l} {$src, $dst|$dst, $src}", [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; // Shift by 1 - def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst), + def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), "shl{b} $dst", [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; - def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst), + def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), "shl{w} $dst", [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, OpSize; - def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst), + def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), "shl{l} $dst", [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; } -def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src), +def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src), "shr{b} {%cl, $dst|$dst, %CL}", [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>; -def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src), +def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src), "shr{w} {%cl, $dst|$dst, %CL}", [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src), +def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src), "shr{l} {%cl, $dst|$dst, %CL}", [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>; -def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), +def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "shr{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; -def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), +def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), "shr{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; -def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), +def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), "shr{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; // Shift by 1 -def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1), +def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), "shr{b} $dst", [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; -def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1), +def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), "shr{w} $dst", [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; -def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1), +def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), "shr{l} $dst", [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; let isTwoAddress = 0 in { - def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), + def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), "shr{b} {%cl, $dst|$dst, %CL}", [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), + def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), "shr{w} {%cl, $dst|$dst, %CL}", [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>, OpSize; - def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), + def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), "shr{l} {%cl, $dst|$dst, %CL}", [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), + def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), "shr{b} {$src, $dst|$dst, $src}", [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; - def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), + def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), "shr{w} {$src, $dst|$dst, $src}", [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, OpSize; - def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), + def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), "shr{l} {$src, $dst|$dst, $src}", [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; // Shift by 1 - def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst), + def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), "shr{b} $dst", [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; - def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst), + def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), "shr{w} $dst", [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; - def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst), + def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), "shr{l} $dst", [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; } -def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src), +def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src), "sar{b} {%cl, $dst|$dst, %CL}", [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>; -def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src), +def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src), "sar{w} {%cl, $dst|$dst, %CL}", [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src), +def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src), "sar{l} {%cl, $dst|$dst, %CL}", [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>; -def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), +def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), "sar{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; -def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), +def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), "sar{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, OpSize; -def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), +def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), "sar{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; // Shift by 1 -def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1), +def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), "sar{b} $dst", [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; -def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1), +def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), "sar{w} $dst", [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; -def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1), +def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), "sar{l} $dst", [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; let isTwoAddress = 0 in { - def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), + def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), "sar{b} {%cl, $dst|$dst, %CL}", [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), + def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), "sar{w} {%cl, $dst|$dst, %CL}", [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>, OpSize; - def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), + def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), "sar{l} {%cl, $dst|$dst, %CL}", [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), + def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), "sar{b} {$src, $dst|$dst, $src}", [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; - def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), + def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), "sar{w} {$src, $dst|$dst, $src}", [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, OpSize; - def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), + def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), "sar{l} {$src, $dst|$dst, $src}", [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; // Shift by 1 - def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst), + def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), "sar{b} $dst", [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; - def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst), + def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), "sar{w} $dst", [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, OpSize; - def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst), + def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), "sar{l} $dst", [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; } // Rotate instructions // FIXME: provide shorter instructions when imm8 == 1 -def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src), +def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "rol{b} {%cl, $dst|$dst, %CL}", [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>; -def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src), +def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src), "rol{w} {%cl, $dst|$dst, %CL}", [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src), +def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src), "rol{l} {%cl, $dst|$dst, %CL}", [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>; -def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), +def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), "rol{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; -def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), +def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), "rol{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize; -def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), +def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), "rol{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; // Rotate by 1 -def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1), +def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), "rol{b} $dst", [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; -def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1), +def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), "rol{w} $dst", [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; -def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1), +def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), "rol{l} $dst", [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; let isTwoAddress = 0 in { - def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), + def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), "rol{b} {%cl, $dst|$dst, %CL}", [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), + def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), "rol{w} {%cl, $dst|$dst, %CL}", [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>, OpSize; - def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), + def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), "rol{l} {%cl, $dst|$dst, %CL}", [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), + def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src), "rol{b} {$src, $dst|$dst, $src}", [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; - def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), + def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src), "rol{w} {$src, $dst|$dst, $src}", [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, OpSize; - def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), + def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src), "rol{l} {$src, $dst|$dst, $src}", [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; // Rotate by 1 - def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst), + def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), "rol{b} $dst", [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; - def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst), + def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), "rol{w} $dst", [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, OpSize; - def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst), + def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), "rol{l} $dst", [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; } -def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src), +def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "ror{b} {%cl, $dst|$dst, %CL}", [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>; -def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src), +def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src), "ror{w} {%cl, $dst|$dst, %CL}", [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src), +def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src), "ror{l} {%cl, $dst|$dst, %CL}", [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>; -def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), +def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), "ror{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; -def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), +def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), "ror{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize; -def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), +def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), "ror{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; // Rotate by 1 -def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1), +def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), "ror{b} $dst", [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; -def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1), +def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), "ror{w} $dst", [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; -def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1), +def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), "ror{l} $dst", [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; let isTwoAddress = 0 in { - def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), + def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), "ror{b} {%cl, $dst|$dst, %CL}", [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), + def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), "ror{w} {%cl, $dst|$dst, %CL}", [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>, OpSize; - def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), + def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), "ror{l} {%cl, $dst|$dst, %CL}", [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; - def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), + def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), "ror{b} {$src, $dst|$dst, $src}", [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; - def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), + def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), "ror{w} {$src, $dst|$dst, $src}", [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, OpSize; - def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), + def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), "ror{l} {$src, $dst|$dst, $src}", [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; // Rotate by 1 - def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst), + def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), "ror{b} $dst", [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; - def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst), + def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), "ror{w} $dst", [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, OpSize; - def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst), + def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), "ror{l} $dst", [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; } @@ -1755,44 +1760,44 @@ let isTwoAddress = 0 in { // Double shift instructions (generalizations of rotate) -def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, Imp<[CL],[]>, TB; -def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, Imp<[CL],[]>, TB; -def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), +def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, Imp<[CL],[]>, TB, OpSize; -def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), +def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, Imp<[CL],[]>, TB, OpSize; let isCommutable = 1 in { // These instructions commute to each other. def SHLD32rri8 : Ii8<0xA4, MRMDestReg, - (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, (i8 imm:$src3)))]>, TB; def SHRD32rri8 : Ii8<0xAC, MRMDestReg, - (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3), + (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, (i8 imm:$src3)))]>, TB; def SHLD16rri8 : Ii8<0xA4, MRMDestReg, - (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, (i8 imm:$src3)))]>, TB, OpSize; def SHRD16rri8 : Ii8<0xAC, MRMDestReg, - (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3), + (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, (i8 imm:$src3)))]>, @@ -1800,47 +1805,47 @@ def SHRD16rri8 : Ii8<0xAC, MRMDestReg, } let isTwoAddress = 0 in { - def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2), + def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB; - def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2), + def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB; def SHLD32mri8 : Ii8<0xA4, MRMDestMem, - (ops i32mem:$dst, GR32:$src2, i8imm:$src3), + (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", [(store (X86shld (loadi32 addr:$dst), GR32:$src2, (i8 imm:$src3)), addr:$dst)]>, TB; def SHRD32mri8 : Ii8<0xAC, MRMDestMem, - (ops i32mem:$dst, GR32:$src2, i8imm:$src3), + (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, (i8 imm:$src3)), addr:$dst)]>, TB; - def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2), + def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB, OpSize; - def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2), + def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB, OpSize; def SHLD16mri8 : Ii8<0xA4, MRMDestMem, - (ops i16mem:$dst, GR16:$src2, i8imm:$src3), + (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", [(store (X86shld (loadi16 addr:$dst), GR16:$src2, (i8 imm:$src3)), addr:$dst)]>, TB, OpSize; def SHRD16mri8 : Ii8<0xAC, MRMDestMem, - (ops i16mem:$dst, GR16:$src2, i8imm:$src3), + (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, (i8 imm:$src3)), addr:$dst)]>, @@ -1850,211 +1855,211 @@ let isTwoAddress = 0 in { // Arithmetic. let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y -def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), +def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), "add{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), +def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize; -def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; } // end isConvertibleToThreeAddress } // end isCommutable -def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), +def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), "add{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>; -def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), +def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize; -def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), +def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>; -def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), +def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "add{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), +def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize; -def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), +def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>; -def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), +def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize; -def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), +def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>; } let isTwoAddress = 0 in { - def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), + def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), "add{b} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>; - def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2), + def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>, OpSize; - def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2), + def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>; - def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), + def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), "add{b} {$src2, $dst|$dst, $src2}", [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; - def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), + def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, OpSize; - def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), + def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; - def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), + def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), "add{w} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, OpSize; - def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), + def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "add{l} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y -def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; } -def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2), +def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; -def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), +def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; -def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), +def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2), + def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; - def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), + def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; - def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2), + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), +def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), "sub{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>; -def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), +def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize; -def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; -def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), +def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), "sub{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>; -def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), +def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize; -def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), +def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>; -def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), +def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}", [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>; -def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), +def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize; -def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), +def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>; -def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), +def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>, OpSize; -def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), +def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), + def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), "sub{b} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>; - def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2), + def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>, OpSize; - def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2), + def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>; - def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), + def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}", [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; - def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), + def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, OpSize; - def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), + def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; - def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), + def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), "sub{w} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, OpSize; - def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), + def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; let isTwoAddress = 0 in { - def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2), + def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; - def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), + def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), "sbb{b} {$src2, $dst|$dst, $src2}", [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; - def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), + def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; - def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2), + def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), +def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; -def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), +def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; -def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), +def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y -def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), +def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "imul{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize; -def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), +def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "imul{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB; } -def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), +def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "imul{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>, TB, OpSize; -def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), +def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "imul{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB; @@ -2062,39 +2067,39 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), // Suprisingly enough, these are not two address instructions! def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 - (ops GR16:$dst, GR16:$src1, i16imm:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize; def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 - (ops GR32:$dst, GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>; def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 - (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), + (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>, OpSize; def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 - (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>; def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 - (ops GR16:$dst, i16mem:$src1, i16imm:$src2), + (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>, OpSize; def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 - (ops GR32:$dst, i32mem:$src1, i32imm:$src2), + (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>; def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 - (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2), + (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, OpSize; def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 - (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2), + (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; @@ -2102,328 +2107,328 @@ def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 // Test instructions are just like AND, except they don't generate a result. // let isCommutable = 1 in { // TEST X, Y --> TEST Y, X -def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2), +def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2), "test{b} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>; -def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2), +def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), "test{w} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize; -def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2), +def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), "test{l} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>; } -def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2), +def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), "test{b} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>; -def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2), +def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), "test{w} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>, OpSize; -def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2), +def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), "test{l} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>; def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 - (ops GR8:$src1, i8imm:$src2), + (outs), (ins GR8:$src1, i8imm:$src2), "test{b} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR8:$src1, imm:$src2), 0)]>; def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 - (ops GR16:$src1, i16imm:$src2), + (outs), (ins GR16:$src1, i16imm:$src2), "test{w} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize; def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 - (ops GR32:$src1, i32imm:$src2), + (outs), (ins GR32:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR32:$src1, imm:$src2), 0)]>; def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 - (ops i8mem:$src1, i8imm:$src2), + (outs), (ins i8mem:$src1, i8imm:$src2), "test{b} {$src2, $src1|$src1, $src2}", [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>; def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 - (ops i16mem:$src1, i16imm:$src2), + (outs), (ins i16mem:$src1, i16imm:$src2), "test{w} {$src2, $src1|$src1, $src2}", [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>, OpSize; def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 - (ops i32mem:$src1, i32imm:$src2), + (outs), (ins i32mem:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>; // Condition code ops, incl. set if equal/not equal/... -def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH -def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags +def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, Imp<[AH],[]>; // flags = AH +def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, Imp<[],[AH]>; // AH = flags def SETEr : I<0x94, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "sete $dst", [(set GR8:$dst, (X86setcc X86_COND_E))]>, TB; // GR8 = == def SETEm : I<0x94, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "sete $dst", [(store (X86setcc X86_COND_E), addr:$dst)]>, TB; // [mem8] = == def SETNEr : I<0x95, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setne $dst", [(set GR8:$dst, (X86setcc X86_COND_NE))]>, TB; // GR8 = != def SETNEm : I<0x95, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setne $dst", [(store (X86setcc X86_COND_NE), addr:$dst)]>, TB; // [mem8] = != def SETLr : I<0x9C, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setl $dst", [(set GR8:$dst, (X86setcc X86_COND_L))]>, TB; // GR8 = < signed def SETLm : I<0x9C, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setl $dst", [(store (X86setcc X86_COND_L), addr:$dst)]>, TB; // [mem8] = < signed def SETGEr : I<0x9D, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setge $dst", [(set GR8:$dst, (X86setcc X86_COND_GE))]>, TB; // GR8 = >= signed def SETGEm : I<0x9D, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setge $dst", [(store (X86setcc X86_COND_GE), addr:$dst)]>, TB; // [mem8] = >= signed def SETLEr : I<0x9E, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setle $dst", [(set GR8:$dst, (X86setcc X86_COND_LE))]>, TB; // GR8 = <= signed def SETLEm : I<0x9E, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setle $dst", [(store (X86setcc X86_COND_LE), addr:$dst)]>, TB; // [mem8] = <= signed def SETGr : I<0x9F, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setg $dst", [(set GR8:$dst, (X86setcc X86_COND_G))]>, TB; // GR8 = > signed def SETGm : I<0x9F, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setg $dst", [(store (X86setcc X86_COND_G), addr:$dst)]>, TB; // [mem8] = > signed def SETBr : I<0x92, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setb $dst", [(set GR8:$dst, (X86setcc X86_COND_B))]>, TB; // GR8 = < unsign def SETBm : I<0x92, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setb $dst", [(store (X86setcc X86_COND_B), addr:$dst)]>, TB; // [mem8] = < unsign def SETAEr : I<0x93, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setae $dst", [(set GR8:$dst, (X86setcc X86_COND_AE))]>, TB; // GR8 = >= unsign def SETAEm : I<0x93, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setae $dst", [(store (X86setcc X86_COND_AE), addr:$dst)]>, TB; // [mem8] = >= unsign def SETBEr : I<0x96, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setbe $dst", [(set GR8:$dst, (X86setcc X86_COND_BE))]>, TB; // GR8 = <= unsign def SETBEm : I<0x96, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setbe $dst", [(store (X86setcc X86_COND_BE), addr:$dst)]>, TB; // [mem8] = <= unsign def SETAr : I<0x97, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "seta $dst", [(set GR8:$dst, (X86setcc X86_COND_A))]>, TB; // GR8 = > signed def SETAm : I<0x97, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "seta $dst", [(store (X86setcc X86_COND_A), addr:$dst)]>, TB; // [mem8] = > signed def SETSr : I<0x98, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "sets $dst", [(set GR8:$dst, (X86setcc X86_COND_S))]>, TB; // GR8 = <sign bit> def SETSm : I<0x98, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "sets $dst", [(store (X86setcc X86_COND_S), addr:$dst)]>, TB; // [mem8] = <sign bit> def SETNSr : I<0x99, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setns $dst", [(set GR8:$dst, (X86setcc X86_COND_NS))]>, TB; // GR8 = !<sign bit> def SETNSm : I<0x99, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setns $dst", [(store (X86setcc X86_COND_NS), addr:$dst)]>, TB; // [mem8] = !<sign bit> def SETPr : I<0x9A, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setp $dst", [(set GR8:$dst, (X86setcc X86_COND_P))]>, TB; // GR8 = parity def SETPm : I<0x9A, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setp $dst", [(store (X86setcc X86_COND_P), addr:$dst)]>, TB; // [mem8] = parity def SETNPr : I<0x9B, MRM0r, - (ops GR8 :$dst), + (outs GR8 :$dst), (ins), "setnp $dst", [(set GR8:$dst, (X86setcc X86_COND_NP))]>, TB; // GR8 = not parity def SETNPm : I<0x9B, MRM0m, - (ops i8mem:$dst), + (outs), (ins i8mem:$dst), "setnp $dst", [(store (X86setcc X86_COND_NP), addr:$dst)]>, TB; // [mem8] = not parity // Integer comparisons def CMP8rr : I<0x38, MRMDestReg, - (ops GR8 :$src1, GR8 :$src2), + (outs), (ins GR8 :$src1, GR8 :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", [(X86cmp GR8:$src1, GR8:$src2)]>; def CMP16rr : I<0x39, MRMDestReg, - (ops GR16:$src1, GR16:$src2), + (outs), (ins GR16:$src1, GR16:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize; def CMP32rr : I<0x39, MRMDestReg, - (ops GR32:$src1, GR32:$src2), + (outs), (ins GR32:$src1, GR32:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp GR32:$src1, GR32:$src2)]>; def CMP8mr : I<0x38, MRMDestMem, - (ops i8mem :$src1, GR8 :$src2), + (outs), (ins i8mem :$src1, GR8 :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>; def CMP16mr : I<0x39, MRMDestMem, - (ops i16mem:$src1, GR16:$src2), + (outs), (ins i16mem:$src1, GR16:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize; def CMP32mr : I<0x39, MRMDestMem, - (ops i32mem:$src1, GR32:$src2), + (outs), (ins i32mem:$src1, GR32:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>; def CMP8rm : I<0x3A, MRMSrcMem, - (ops GR8 :$src1, i8mem :$src2), + (outs), (ins GR8 :$src1, i8mem :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>; def CMP16rm : I<0x3B, MRMSrcMem, - (ops GR16:$src1, i16mem:$src2), + (outs), (ins GR16:$src1, i16mem:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize; def CMP32rm : I<0x3B, MRMSrcMem, - (ops GR32:$src1, i32mem:$src2), + (outs), (ins GR32:$src1, i32mem:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>; def CMP8ri : Ii8<0x80, MRM7r, - (ops GR8:$src1, i8imm:$src2), + (outs), (ins GR8:$src1, i8imm:$src2), "cmp{b} {$src2, $src1|$src1, $src2}", [(X86cmp GR8:$src1, imm:$src2)]>; def CMP16ri : Ii16<0x81, MRM7r, - (ops GR16:$src1, i16imm:$src2), + (outs), (ins GR16:$src1, i16imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp GR16:$src1, imm:$src2)]>, OpSize; def CMP32ri : Ii32<0x81, MRM7r, - (ops GR32:$src1, i32imm:$src2), + (outs), (ins GR32:$src1, i32imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp GR32:$src1, imm:$src2)]>; def CMP8mi : Ii8 <0x80, MRM7m, - (ops i8mem :$src1, i8imm :$src2), + (outs), (ins i8mem :$src1, i8imm :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi8 addr:$src1), imm:$src2)]>; def CMP16mi : Ii16<0x81, MRM7m, - (ops i16mem:$src1, i16imm:$src2), + (outs), (ins i16mem:$src1, i16imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize; def CMP32mi : Ii32<0x81, MRM7m, - (ops i32mem:$src1, i32imm:$src2), + (outs), (ins i32mem:$src1, i32imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi32 addr:$src1), imm:$src2)]>; def CMP16ri8 : Ii8<0x83, MRM7r, - (ops GR16:$src1, i16i8imm:$src2), + (outs), (ins GR16:$src1, i16i8imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize; def CMP16mi8 : Ii8<0x83, MRM7m, - (ops i16mem:$src1, i16i8imm:$src2), + (outs), (ins i16mem:$src1, i16i8imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize; def CMP32mi8 : Ii8<0x83, MRM7m, - (ops i32mem:$src1, i32i8imm:$src2), + (outs), (ins i32mem:$src1, i32i8imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>; def CMP32ri8 : Ii8<0x83, MRM7r, - (ops GR32:$src1, i32i8imm:$src2), + (outs), (ins GR32:$src1, i32i8imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp GR32:$src1, i32immSExt8:$src2)]>; // Sign/Zero extenders -def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src), +def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), "movs{bw|x} {$src, $dst|$dst, $src}", [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize; -def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src), +def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), "movs{bw|x} {$src, $dst|$dst, $src}", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; -def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src), +def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), "movs{bl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (sext GR8:$src))]>, TB; -def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src), +def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), "movs{bl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; -def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src), +def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), "movs{wl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (sext GR16:$src))]>, TB; -def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src), +def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), "movs{wl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; -def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src), +def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), "movz{bw|x} {$src, $dst|$dst, $src}", [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize; -def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src), +def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), "movz{bw|x} {$src, $dst|$dst, $src}", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; -def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src), +def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), "movz{bl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (zext GR8:$src))]>, TB; -def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src), +def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), "movz{bl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; -def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src), +def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), "movz{wl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (zext GR16:$src))]>, TB; -def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src), +def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), "movz{wl|x} {$src, $dst|$dst, $src}", [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; -def CBW : I<0x98, RawFrm, (ops), +def CBW : I<0x98, RawFrm, (outs), (ins), "{cbtw|cbw}", []>, Imp<[AL],[AX]>, OpSize; // AX = signext(AL) -def CWDE : I<0x98, RawFrm, (ops), +def CWDE : I<0x98, RawFrm, (outs), (ins), "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX) -def CWD : I<0x99, RawFrm, (ops), +def CWD : I<0x99, RawFrm, (outs), (ins), "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>, OpSize; // DX:AX = signext(AX) -def CDQ : I<0x99, RawFrm, (ops), +def CDQ : I<0x99, RawFrm, (outs), (ins), "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX) @@ -2433,57 +2438,57 @@ def CDQ : I<0x99, RawFrm, (ops), // Alias instructions that map movr0 to xor. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. -def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst), +def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "xor{b} $dst, $dst", [(set GR8:$dst, 0)]>; -def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst), +def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), "xor{w} $dst, $dst", [(set GR16:$dst, 0)]>, OpSize; -def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst), +def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "xor{l} $dst, $dst", [(set GR32:$dst, 0)]>; // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX). -def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src), +def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src), +def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src), +def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src), +def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src), +def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src), +def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src), +def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src), +def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src), "mov{l} {$src, $dst|$dst, $src}", []>; //===----------------------------------------------------------------------===// // Thread Local Storage Instructions // -def TLS_addr : I<0, Pseudo, (ops GR32:$dst, i32imm:$sym), +def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym), "leal ${sym:mem}(,%ebx,1), $dst", [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>, Imp<[EBX],[]>; let AddedComplexity = 10 in -def TLS_gs_rr : I<0, Pseudo, (ops GR32:$dst, GR32:$src), +def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), "movl %gs:($src), $dst", [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>; let AddedComplexity = 15 in -def TLS_gs_ri : I<0, Pseudo, (ops GR32:$dst, i32imm:$src), +def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src), "movl %gs:${src:mem}, $dst", [(set GR32:$dst, (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>; -def TLS_tp : I<0, Pseudo, (ops GR32:$dst), +def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins), "movl %gs:0, $dst", [(set GR32:$dst, X86TLStp)]>; @@ -2491,7 +2496,8 @@ def TLS_tp : I<0, Pseudo, (ops GR32:$dst), // DWARF Pseudo Instructions // -def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file), +def DWARF_LOC : I<0, Pseudo, (outs), + (ins i32imm:$line, i32imm:$col, i32imm:$file), "; .loc $file, $line, $col", [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; @@ -2501,7 +2507,7 @@ def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file), // let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1, noResults = 1 in { -def EH_RETURN : I<0xC3, RawFrm, (ops GR32:$addr), +def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), "ret #eh_return, addr: $addr", [(X86ehret GR32:$addr)]>; diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index c77446017d..eed8843b38 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -23,21 +23,21 @@ // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. -class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>; -class MMXRI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TB, REX_W, Requires<[HasMMX]>; -class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>; -class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>; -class MMXID<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii8<o, F, ops, asm, pattern>, XD, Requires<[HasMMX]>; -class MMXIS<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii8<o, F, ops, asm, pattern>, XS, Requires<[HasMMX]>; +class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>; +class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>; +class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>; +class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>; +class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>; +class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>; // Some 'special' instructions -def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst), +def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins), "#IMPLICIT_DEF $dst", [(set VR64:$dst, (v8i8 (undef)))]>, Requires<[HasMMX]>; @@ -107,12 +107,12 @@ let isTwoAddress = 1 in { // MMXI_binop_rm - Simple MMX binary operator. multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, ValueType OpVT, bit Commutable = 0> { - def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2), + def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> { let isCommutable = Commutable; } - def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2), + def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (OpVT (OpNode VR64:$src1, (bitconvert @@ -121,12 +121,12 @@ let isTwoAddress = 1 in { multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, bit Commutable = 0> { - def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2), + def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> { let isCommutable = Commutable; } - def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2), + def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, (bitconvert (load_mmx addr:$src2))))]>; @@ -139,12 +139,12 @@ let isTwoAddress = 1 in { // multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2), + def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> { let isCommutable = Commutable; } - def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2), + def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (OpNode VR64:$src1,(load_mmx addr:$src2)))]>; @@ -152,14 +152,14 @@ let isTwoAddress = 1 in { multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, string OpcodeStr, Intrinsic IntId> { - def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2), + def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>; - def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2), + def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, (bitconvert (load_mmx addr:$src2))))]>; - def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2), + def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, (scalar_to_vector (i32 imm:$src2))))]>; @@ -170,58 +170,58 @@ let isTwoAddress = 1 in { // MMX EMMS & FEMMS Instructions //===----------------------------------------------------------------------===// -def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>; -def MMX_FEMMS : MMXI<0x0E, RawFrm, (ops), "femms", [(int_x86_mmx_femms)]>; +def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>; +def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>; //===----------------------------------------------------------------------===// // MMX Scalar Instructions //===----------------------------------------------------------------------===// // Data Transfer Instructions -def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), +def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), "movd {$src, $dst|$dst, $src}", []>; -def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), +def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), "movd {$src, $dst|$dst, $src}", []>; -def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src), +def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), "movd {$src, $dst|$dst, $src}", []>; -def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (ops VR64:$dst, GR64:$src), +def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), "movd {$src, $dst|$dst, $src}", []>; -def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src), +def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), "movq {$src, $dst|$dst, $src}", []>; -def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src), +def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq {$src, $dst|$dst, $src}", [(set VR64:$dst, (load_mmx addr:$src))]>; -def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src), +def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}", [(store (v1i64 VR64:$src), addr:$dst)]>; -def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src), +def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src), "movdq2q {$src, $dst|$dst, $src}", [(set VR64:$dst, (v1i64 (vector_extract (v2i64 VR128:$src), (iPTR 0))))]>; -def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src), +def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src), "movq2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (bitconvert (v1i64 VR64:$src)))]>; -def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src), +def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movntq {$src, $dst|$dst, $src}", [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>; let AddedComplexity = 15 in // movd to MMX register zero-extends -def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), +def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), "movd {$src, $dst|$dst, $src}", [(set VR64:$dst, (v2i32 (vector_shuffle immAllZerosV, (v2i32 (scalar_to_vector GR32:$src)), MMX_MOVL_shuffle_mask)))]>; let AddedComplexity = 20 in -def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), +def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), "movd {$src, $dst|$dst, $src}", [(set VR64:$dst, (v2i32 (vector_shuffle immAllZerosV, @@ -283,12 +283,12 @@ defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>; let isTwoAddress = 1 in { def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "pandn {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1), VR64:$src2)))]>; def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "pandn {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1), (load addr:$src2))))]>; @@ -329,13 +329,13 @@ defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>; let isTwoAddress = 1 in { // Unpack High Packed Data Instructions def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "punpckhbw {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v8i8 (vector_shuffle VR64:$src1, VR64:$src2, MMX_UNPCKH_shuffle_mask)))]>; def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "punpckhbw {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v8i8 (vector_shuffle VR64:$src1, @@ -343,13 +343,13 @@ let isTwoAddress = 1 in { MMX_UNPCKH_shuffle_mask)))]>; def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "punpckhwd {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v4i16 (vector_shuffle VR64:$src1, VR64:$src2, MMX_UNPCKH_shuffle_mask)))]>; def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "punpckhwd {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v4i16 (vector_shuffle VR64:$src1, @@ -357,13 +357,13 @@ let isTwoAddress = 1 in { MMX_UNPCKH_shuffle_mask)))]>; def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "punpckhdq {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v2i32 (vector_shuffle VR64:$src1, VR64:$src2, MMX_UNPCKH_shuffle_mask)))]>; def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "punpckhdq {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v2i32 (vector_shuffle VR64:$src1, @@ -372,13 +372,13 @@ let isTwoAddress = 1 in { // Unpack Low Packed Data Instructions def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "punpcklbw {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v8i8 (vector_shuffle VR64:$src1, VR64:$src2, MMX_UNPCKL_shuffle_mask)))]>; def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "punpcklbw {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v8i8 (vector_shuffle VR64:$src1, @@ -386,13 +386,13 @@ let isTwoAddress = 1 in { MMX_UNPCKL_shuffle_mask)))]>; def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "punpcklwd {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v4i16 (vector_shuffle VR64:$src1, VR64:$src2, MMX_UNPCKL_shuffle_mask)))]>; def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "punpcklwd {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v4i16 (vector_shuffle VR64:$src1, @@ -400,13 +400,13 @@ let isTwoAddress = 1 in { MMX_UNPCKL_shuffle_mask)))]>; def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, VR64:$src2), + (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), "punpckldq {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v2i32 (vector_shuffle VR64:$src1, VR64:$src2, MMX_UNPCKL_shuffle_mask)))]>; def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i64mem:$src2), + (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), "punpckldq {$src2, $dst|$dst, $src2}", [(set VR64:$dst, (v2i32 (vector_shuffle VR64:$src1, @@ -421,14 +421,14 @@ defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>; // -- Shuffle Instructions def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, i8imm:$src2), + (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2), "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR64:$dst, (v4i16 (vector_shuffle VR64:$src1, (undef), MMX_PSHUFW_shuffle_mask:$src2)))]>; def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, - (ops VR64:$dst, i64mem:$src1, i8imm:$src2), + (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2), "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR64:$dst, (v4i16 (vector_shuffle @@ -437,34 +437,34 @@ def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, MMX_PSHUFW_shuffle_mask:$src2)))]>; // -- Conversion Instructions -def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), +def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src), "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), +def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), "cvtpi2pd {$src, $dst|$dst, $src}", []>; -def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "cvtpi2pd {$src, $dst|$dst, $src}", []>; -def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), +def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), "cvtps2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), +def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), "cvtps2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), "cvttpd2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (ops VR64:$dst, f128mem:$src), +def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src), "cvttpd2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), "cvttps2pi {$src, $dst|$dst, $src}", []>; -def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src), +def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), "cvttps2pi {$src, $dst|$dst, $src}", []>; // Extract / Insert @@ -472,18 +472,18 @@ def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>; def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>; def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg, - (ops GR32:$dst, VR64:$src1, i16i8imm:$src2), + (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2), "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1), (iPTR imm:$src2)))]>; let isTwoAddress = 1 in { def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, GR32:$src2, i16i8imm:$src3), + (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1), GR32:$src2, (iPTR imm:$src3))))]>; def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem, - (ops VR64:$dst, VR64:$src1, i16mem:$src2, i16i8imm:$src3), + (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1), @@ -492,12 +492,12 @@ let isTwoAddress = 1 in { } // Mask creation -def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (ops GR32:$dst, VR64:$src), +def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src), "pmovmskb {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>; // Misc. -def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask), +def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask), "maskmovq {$mask, $src|$src, $mask}", [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>, Imp<[EDI],[]>; @@ -509,10 +509,10 @@ def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask), // Alias instructions that map zero vector to pxor. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. let isReMaterializable = 1 in { - def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst), + def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins), "pxor $dst, $dst", [(set VR64:$dst, (v1i64 immAllZerosV))]>; - def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst), + def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins), "pcmpeqd $dst, $dst", [(set VR64:$dst, (v1i64 immAllOnesV))]>; } diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index f2466b5efb..fdae446543 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -46,14 +46,14 @@ def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>; // SSE 'Special' Instructions //===----------------------------------------------------------------------===// -def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst), +def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins), "#IMPLICIT_DEF $dst", [(set VR128:$dst, (v4f32 (undef)))]>, Requires<[HasSSE1]>; -def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst), +def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins), "#IMPLICIT_DEF $dst", [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>; -def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst), +def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins), "#IMPLICIT_DEF $dst", [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>; @@ -250,25 +250,25 @@ def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{ // scheduler into a branch sequence. let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. def CMOV_FR32 : I<0, Pseudo, - (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond), + (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), "#CMOV_FR32 PSEUDO!", [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>; def CMOV_FR64 : I<0, Pseudo, - (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond), + (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), "#CMOV_FR64 PSEUDO!", [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>; def CMOV_V4F32 : I<0, Pseudo, - (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond), + (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), "#CMOV_V4F32 PSEUDO!", [(set VR128:$dst, (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>; def CMOV_V2F64 : I<0, Pseudo, - (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond), + (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), "#CMOV_V2F64 PSEUDO!", [(set VR128:$dst, (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>; def CMOV_V2I64 : I<0, Pseudo, - (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond), + (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), "#CMOV_V2I64 PSEUDO!", [(set VR128:$dst, (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>; @@ -284,64 +284,65 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. // PSI - SSE1 instructions with TB prefix. // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. -class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>; -class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>; -class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>; +class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; +class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>; +class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>; // Move Instructions -def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src), +def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), "movss {$src, $dst|$dst, $src}", []>; -def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src), +def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), "movss {$src, $dst|$dst, $src}", [(set FR32:$dst, (loadf32 addr:$src))]>; -def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src), +def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src), "movss {$src, $dst|$dst, $src}", [(store FR32:$src, addr:$dst)]>; // Conversion instructions -def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src), +def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src), "cvttss2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (fp_to_sint FR32:$src))]>; -def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src), +def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src), "cvttss2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>; -def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src), +def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), "cvtsi2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (sint_to_fp GR32:$src))]>; -def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src), +def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), "cvtsi2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>; // Match intrinsics which expect XMM operand(s). -def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "cvtss2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>; -def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src), +def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src), "cvtss2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse_cvtss2si (load addr:$src)))]>; // Aliases for intrinsics -def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "cvttss2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>; -def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src), +def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src), "cvttss2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse_cvttss2si(load addr:$src)))]>; let isTwoAddress = 1 in { def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, GR32:$src2), + (outs VR128:$dst), (ins VR128:$src1, GR32:$src2), "cvtsi2ss {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, GR32:$src2))]>; def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i32mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2), "cvtsi2ss {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, (loadi32 addr:$src2)))]>; @@ -350,46 +351,46 @@ let isTwoAddress = 1 in { // Comparison instructions let isTwoAddress = 1 in { def CMPSSrr : SSI<0xC2, MRMSrcReg, - (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc), + (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc), "cmp${cc}ss {$src, $dst|$dst, $src}", []>; def CMPSSrm : SSI<0xC2, MRMSrcMem, - (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc), + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc), "cmp${cc}ss {$src, $dst|$dst, $src}", []>; } -def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2), +def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2), "ucomiss {$src2, $src1|$src1, $src2}", [(X86cmp FR32:$src1, FR32:$src2)]>; -def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2), +def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2), "ucomiss {$src2, $src1|$src1, $src2}", [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>; // Aliases to match intrinsics which expect XMM operand(s). let isTwoAddress = 1 in { def Int_CMPSSrr : SSI<0xC2, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}ss {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, VR128:$src, imm:$cc))]>; def Int_CMPSSrm : SSI<0xC2, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc), "cmp${cc}ss {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, (load addr:$src), imm:$cc))]>; } -def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2), +def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), "ucomiss {$src2, $src1|$src1, $src2}", [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>; -def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), +def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), "ucomiss {$src2, $src1|$src1, $src2}", [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>; -def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2), +def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), "comiss {$src2, $src1|$src1, $src2}", [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>; -def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), +def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), "comiss {$src2, $src1|$src1, $src2}", [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>; @@ -397,53 +398,53 @@ def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), // start with 'Fs'. // Alias instructions that map fld0 to pxor for sse. -def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst), +def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are // disregarded. -def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src), +def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), "movaps {$src, $dst|$dst, $src}", []>; // Alias instruction to load FR32 from f128mem using movaps. Upper bits are // disregarded. -def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src), +def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), "movaps {$src, $dst|$dst, $src}", [(set FR32:$dst, (X86loadpf32 addr:$src))]>; // Alias bitwise logical operations using SSE logical ops on packed FP values. let isTwoAddress = 1 in { let isCommutable = 1 in { - def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), "andps {$src2, $dst|$dst, $src2}", [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>; - def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), "orps {$src2, $dst|$dst, $src2}", [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>; - def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), "xorps {$src2, $dst|$dst, $src2}", [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>; } -def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2), +def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2), "andps {$src2, $dst|$dst, $src2}", [(set FR32:$dst, (X86fand FR32:$src1, (X86loadpf32 addr:$src2)))]>; -def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2), +def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2), "orps {$src2, $dst|$dst, $src2}", [(set FR32:$dst, (X86for FR32:$src1, (X86loadpf32 addr:$src2)))]>; -def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2), +def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2), "xorps {$src2, $dst|$dst, $src2}", [(set FR32:$dst, (X86fxor FR32:$src1, (X86loadpf32 addr:$src2)))]>; def FsANDNPSrr : PSI<0x55, MRMSrcReg, - (ops FR32:$dst, FR32:$src1, FR32:$src2), + (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), "andnps {$src2, $dst|$dst, $src2}", []>; def FsANDNPSrm : PSI<0x55, MRMSrcMem, - (ops FR32:$dst, FR32:$src1, f128mem:$src2), + (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2), "andnps {$src2, $dst|$dst, $src2}", []>; } @@ -462,38 +463,38 @@ multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, bit Commutable = 0> { // Scalar operation, reg+reg. - def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> { let isCommutable = Commutable; } // Scalar operation, reg+mem. - def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), + def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>; // Vector operation, reg+reg. - def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> { let isCommutable = Commutable; } // Vector operation, reg+mem. - def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), + def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>; // Intrinsic operation, reg+reg. - def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } // Intrinsic operation, reg+mem. - def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2), + def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F32Int VR128:$src1, sse_load_f32:$src2))]>; @@ -523,51 +524,51 @@ multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, bit Commutable = 0> { // Scalar operation, reg+reg. - def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> { let isCommutable = Commutable; } // Scalar operation, reg+mem. - def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), + def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>; // Vector operation, reg+reg. - def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> { let isCommutable = Commutable; } // Vector operation, reg+mem. - def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), + def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>; // Intrinsic operation, reg+reg. - def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } // Intrinsic operation, reg+mem. - def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2), + def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2), !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F32Int VR128:$src1, sse_load_f32:$src2))]>; // Vector intrinsic operation, reg+reg. - def PSrr_Int : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } // Vector intrinsic operation, reg+mem. - def PSrm_Int : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), + def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2), !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>; } @@ -582,44 +583,44 @@ defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin, // SSE packed FP Instructions // Move Instructions -def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movaps {$src, $dst|$dst, $src}", []>; -def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movaps {$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>; -def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movaps {$src, $dst|$dst, $src}", [(alignedstore (v4f32 VR128:$src), addr:$dst)]>; -def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movups {$src, $dst|$dst, $src}", []>; -def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups {$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv4f32 addr:$src))]>; -def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movups {$src, $dst|$dst, $src}", [(store (v4f32 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPS load and store -def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; -def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movups {$src, $dst|$dst, $src}", [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>; let isTwoAddress = 1 in { let AddedComplexity = 20 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), "movlps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))), MOVLP_shuffle_mask)))]>; def MOVHPSrm : PSI<0x16, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), "movhps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, @@ -628,14 +629,14 @@ let isTwoAddress = 1 in { } // AddedComplexity } // isTwoAddress -def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), +def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movlps {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)), (iPTR 0))), addr:$dst)]>; // v2f64 extract element 1 is always custom lowered to unpack high to low // and extract element 0 so the non-store version isn't too horrible. -def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), +def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movhps {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (v2f64 (vector_shuffle @@ -645,13 +646,13 @@ def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), let isTwoAddress = 1 in { let AddedComplexity = 15 in { -def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), +def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "movlhps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, MOVHP_shuffle_mask)))]>; -def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), +def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "movhlps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, @@ -681,50 +682,50 @@ multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr, Intrinsic V4F32Int, bit Commutable = 0> { // Scalar operation, reg. - def SSr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src), + def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"), [(set FR32:$dst, (OpNode FR32:$src))]> { let isCommutable = Commutable; } // Scalar operation, mem. - def SSm : SSI<opc, MRMSrcMem, (ops FR32:$dst, f32mem:$src), + def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"), [(set FR32:$dst, (OpNode (load addr:$src)))]>; // Vector operation, reg. - def PSr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src), + def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"), [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> { let isCommutable = Commutable; } // Vector operation, mem. - def PSm : PSI<opc, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"), [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>; // Intrinsic operation, reg. - def SSr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src), + def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"), [(set VR128:$dst, (F32Int VR128:$src))]> { let isCommutable = Commutable; } // Intrinsic operation, mem. - def SSm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, ssmem:$src), + def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src), !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"), [(set VR128:$dst, (F32Int sse_load_f32:$src))]>; // Vector intrinsic operation, reg - def PSr_Int : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src), + def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"), [(set VR128:$dst, (V4F32Int VR128:$src))]> { let isCommutable = Commutable; } // Vector intrinsic operation, mem - def PSm_Int : PSI<opc, MRMSrcMem, (ops VR128:$dst, f32mem:$src), + def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"), [(set VR128:$dst, (V4F32Int (load addr:$src)))]>; } @@ -744,46 +745,46 @@ defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp, let isTwoAddress = 1 in { let isCommutable = 1 in { def ANDPSrr : PSI<0x54, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "andps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>; def ORPSrr : PSI<0x56, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "orps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>; def XORPSrr : PSI<0x57, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "xorps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>; } def ANDPSrm : PSI<0x54, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "andps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (and VR128:$src1, (bc_v2i64 (memopv4f32 addr:$src2))))]>; def ORPSrm : PSI<0x56, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "orps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (or VR128:$src1, (bc_v2i64 (memopv4f32 addr:$src2))))]>; def XORPSrm : PSI<0x57, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "xorps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (xor VR128:$src1, (bc_v2i64 (memopv4f32 addr:$src2))))]>; def ANDNPSrr : PSI<0x55, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "andnps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))), VR128:$src2)))]>; def ANDNPSrm : PSI<0x55, MRMSrcMem, - (ops VR128:$dst, VR128:$src1,f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2), "andnps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and (xor VR128:$src1, @@ -793,12 +794,12 @@ let isTwoAddress = 1 in { let isTwoAddress = 1 in { def CMPPSrri : PSIi8<0xC2, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, VR128:$src, imm:$cc))]>; def CMPPSrmi : PSIi8<0xC2, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), "cmp${cc}ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, (load addr:$src), imm:$cc))]>; @@ -808,7 +809,7 @@ let isTwoAddress = 1 in { let isTwoAddress = 1 in { let isConvertibleToThreeAddress = 1 in // Convert to pshufd def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3), "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, @@ -816,7 +817,7 @@ let isTwoAddress = 1 in { VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$src3)))]>; def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2, i32i8imm:$src3), "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, @@ -826,14 +827,14 @@ let isTwoAddress = 1 in { let AddedComplexity = 10 in { def UNPCKHPSrr : PSI<0x15, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "unpckhps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKH_shuffle_mask)))]>; def UNPCKHPSrm : PSI<0x15, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "unpckhps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle @@ -841,14 +842,14 @@ let isTwoAddress = 1 in { UNPCKH_shuffle_mask)))]>; def UNPCKLPSrr : PSI<0x14, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "unpcklps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKL_shuffle_mask)))]>; def UNPCKLPSrm : PSI<0x14, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "unpcklps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle @@ -858,47 +859,47 @@ let isTwoAddress = 1 in { } // isTwoAddress // Mask creation -def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "movmskps {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>; -def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "movmskpd {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>; // Prefetching loads. // TODO: no intrinsics for these? -def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>; -def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>; -def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>; -def PREFETCHNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchnta $src", []>; +def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0 $src", []>; +def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1 $src", []>; +def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2 $src", []>; +def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta $src", []>; // Non-temporal stores -def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), +def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movntps {$src, $dst|$dst, $src}", [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; // Load, store, and memory fence -def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>; +def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>; // MXCSR register -def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src), +def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src), "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>; -def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst), +def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst), "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>; // Alias instructions that map zero vector to pxor / xorp* for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. let isReMaterializable = 1 in -def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst), +def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "xorps $dst, $dst", [(set VR128:$dst, (v4f32 immAllZerosV))]>; // FR32 to 128-bit vector conversion. -def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src), +def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src), "movss {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (scalar_to_vector FR32:$src)))]>; -def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), +def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), "movss {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>; @@ -908,11 +909,11 @@ def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), // like this: // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), // (f32 FR32:$src)>; -def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src), +def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src), "movss {$src, $dst|$dst, $src}", [(set FR32:$dst, (vector_extract (v4f32 VR128:$src), (iPTR 0)))]>; -def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src), +def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src), "movss {$src, $dst|$dst, $src}", [(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), addr:$dst)]>; @@ -922,12 +923,12 @@ def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src), // Three operand (but two address) aliases. let isTwoAddress = 1 in { def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, FR32:$src2), + (outs VR128:$dst), (ins VR128:$src1, FR32:$src2), "movss {$src2, $dst|$dst, $src2}", []>; let AddedComplexity = 15 in def MOVLPSrr : SSI<0x10, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "movss {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, @@ -937,7 +938,7 @@ let isTwoAddress = 1 in { // Move to lower bits of a VR128 and zeroing upper bits. // Loading from memory automatically zeroing upper bits. let AddedComplexity = 20 in -def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), +def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), "movss {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV, (v4f32 (scalar_to_vector (loadf32 addr:$src))), @@ -954,68 +955,69 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), // PDI - SSE2 instructions with TB and OpSize prefixes. // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. -class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>; -class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; -class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; +class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>; +class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; +class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; // Move Instructions -def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src), +def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), "movsd {$src, $dst|$dst, $src}", []>; -def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src), +def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src), "movsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (loadf64 addr:$src))]>; -def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src), +def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src), "movsd {$src, $dst|$dst, $src}", [(store FR64:$src, addr:$dst)]>; // Conversion instructions -def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src), +def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src), "cvttsd2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (fp_to_sint FR64:$src))]>; -def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src), +def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src), "cvttsd2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>; -def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src), +def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src), "cvtsd2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (fround FR64:$src))]>; -def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), +def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src), "cvtsd2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (fround (loadf64 addr:$src)))]>; -def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src), +def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src), "cvtsi2sd {$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp GR32:$src))]>; -def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src), +def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src), "cvtsi2sd {$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>; // SSE2 instructions with XS prefix -def CVTSS2SDrr : I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), +def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), "cvtss2sd {$src, $dst|$dst, $src}", [(set FR64:$dst, (fextend FR32:$src))]>, XS, Requires<[HasSSE2]>; -def CVTSS2SDrm : I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), +def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src), "cvtss2sd {$src, $dst|$dst, $src}", [(set FR64:$dst, (extloadf32 addr:$src))]>, XS, Requires<[HasSSE2]>; // Match intrinsics which expect XMM operand(s). -def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "cvtsd2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; -def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src), +def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src), "cvtsd2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_cvtsd2si (load addr:$src)))]>; // Aliases for intrinsics -def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "cvttsd2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>; -def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src), +def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src), "cvttsd2si {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_cvttsd2si (load addr:$src)))]>; @@ -1023,45 +1025,45 @@ def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src), // Comparison instructions let isTwoAddress = 1 in { def CMPSDrr : SDI<0xC2, MRMSrcReg, - (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc), + (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc), "cmp${cc}sd {$src, $dst|$dst, $src}", []>; def CMPSDrm : SDI<0xC2, MRMSrcMem, - (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc), + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc), "cmp${cc}sd {$src, $dst|$dst, $src}", []>; } -def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2), +def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2), "ucomisd {$src2, $src1|$src1, $src2}", [(X86cmp FR64:$src1, FR64:$src2)]>; -def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2), +def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2), "ucomisd {$src2, $src1|$src1, $src2}", [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>; // Aliases to match intrinsics which expect XMM operand(s). let isTwoAddress = 1 in { def Int_CMPSDrr : SDI<0xC2, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}sd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1, VR128:$src, imm:$cc))]>; def Int_CMPSDrm : SDI<0xC2, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc), "cmp${cc}sd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1, (load addr:$src), imm:$cc))]>; } -def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2), +def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), "ucomisd {$src2, $src1|$src1, $src2}", [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>; -def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), +def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), "ucomisd {$src2, $src1|$src1, $src2}", [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>; -def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2), +def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), "comisd {$src2, $src1|$src1, $src2}", [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>; -def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), +def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), "comisd {$src2, $src1|$src1, $src2}", [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>; @@ -1069,53 +1071,53 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), // start with 'Fs'. // Alias instructions that map fld0 to pxor for sse. -def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst), +def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "pxor $dst, $dst", [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>, TB, OpSize; // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are // disregarded. -def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src), +def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), "movapd {$src, $dst|$dst, $src}", []>; // Alias instruction to load FR64 from f128mem using movapd. Upper bits are // disregarded. -def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src), +def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), "movapd {$src, $dst|$dst, $src}", [(set FR64:$dst, (X86loadpf64 addr:$src))]>; // Alias bitwise logical operations using SSE logical ops on packed FP values. let isTwoAddress = 1 in { let isCommutable = 1 in { - def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), + def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), "andpd {$src2, $dst|$dst, $src2}", [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>; - def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), + def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), "orpd {$src2, $dst|$dst, $src2}", [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>; - def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), + def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), "xorpd {$src2, $dst|$dst, $src2}", [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>; } -def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2), +def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2), "andpd {$src2, $dst|$dst, $src2}", [(set FR64:$dst, (X86fand FR64:$src1, (X86loadpf64 addr:$src2)))]>; -def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2), +def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2), "orpd {$src2, $dst|$dst, $src2}", [(set FR64:$dst, (X86for FR64:$src1, (X86loadpf64 addr:$src2)))]>; -def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2), +def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2), "xorpd {$src2, $dst|$dst, $src2}", [(set FR64:$dst, (X86fxor FR64:$src1, (X86loadpf64 addr:$src2)))]>; def FsANDNPDrr : PDI<0x55, MRMSrcReg, - (ops FR64:$dst, FR64:$src1, FR64:$src2), + (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), "andnpd {$src2, $dst|$dst, $src2}", []>; def FsANDNPDrm : PDI<0x55, MRMSrcMem, - (ops FR64:$dst, FR64:$src1, f128mem:$src2), + (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2), "andnpd {$src2, $dst|$dst, $src2}", []>; } @@ -1134,38 +1136,38 @@ multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic F64Int, bit Commutable = 0> { // Scalar operation, reg+reg. - def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), + def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> { let isCommutable = Commutable; } // Scalar operation, reg+mem. - def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), + def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>; // Vector operation, reg+reg. - def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> { let isCommutable = Commutable; } // Vector operation, reg+mem. - def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), + def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>; // Intrinsic operation, reg+reg. - def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } // Intrinsic operation, reg+mem. - def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2), + def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F64Int VR128:$src1, sse_load_f64:$src2))]>; @@ -1195,51 +1197,51 @@ multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr, bit Commutable = 0> { // Scalar operation, reg+reg. - def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), + def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> { let isCommutable = Commutable; } // Scalar operation, reg+mem. - def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), + def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>; // Vector operation, reg+reg. - def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> { let isCommutable = Commutable; } // Vector operation, reg+mem. - def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), + def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>; // Intrinsic operation, reg+reg. - def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } // Intrinsic operation, reg+mem. - def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2), + def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2), !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (F64Int VR128:$src1, sse_load_f64:$src2))]>; // Vector intrinsic operation, reg+reg. - def PDrr_Int : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } // Vector intrinsic operation, reg+mem. - def PDrm_Int : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), + def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>; } @@ -1254,44 +1256,44 @@ defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin, // SSE packed FP Instructions // Move Instructions -def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movapd {$src, $dst|$dst, $src}", []>; -def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movapd {$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>; -def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movapd {$src, $dst|$dst, $src}", [(alignedstore (v2f64 VR128:$src), addr:$dst)]>; -def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movupd {$src, $dst|$dst, $src}", []>; -def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movupd {$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv2f64 addr:$src))]>; -def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movupd {$src, $dst|$dst, $src}", [(store (v2f64 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPD load and store -def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movupd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>; -def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movupd {$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; let isTwoAddress = 1 in { let AddedComplexity = 20 in { def MOVLPDrm : PDI<0x12, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), "movlpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)), MOVLP_shuffle_mask)))]>; def MOVHPDrm : PDI<0x16, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), "movhpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, @@ -1300,14 +1302,14 @@ let isTwoAddress = 1 in { } // AddedComplexity } // isTwoAddress -def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), +def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movlpd {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), addr:$dst)]>; // v2f64 extract element 1 is always custom lowered to unpack high to low // and extract element 0 so the non-store version isn't too horrible. -def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), +def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movhpd {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (v2f64 (vector_shuffle VR128:$src, (undef), @@ -1315,79 +1317,79 @@ def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), addr:$dst)]>; // SSE2 instructions without OpSize prefix -def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtdq2ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>, TB, Requires<[HasSSE2]>; -def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src), +def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "cvtdq2ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2ps (bitconvert (memopv2i64 addr:$src))))]>, TB, Requires<[HasSSE2]>; // SSE2 instructions with XS prefix -def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtdq2pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>, XS, Requires<[HasSSE2]>; -def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "cvtdq2pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2pd (bitconvert (memopv2i64 addr:$src))))]>, XS, Requires<[HasSSE2]>; -def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>; -def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvtps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2dq (load addr:$src)))]>; // SSE2 packed instructions with XS prefix -def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvttps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>, XS, Requires<[HasSSE2]>; -def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvttps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttps2dq (load addr:$src)))]>, XS, Requires<[HasSSE2]>; // SSE2 packed instructions with XD prefix -def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>, XD, Requires<[HasSSE2]>; -def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvtpd2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2dq (load addr:$src)))]>, XD, Requires<[HasSSE2]>; -def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvttpd2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>; -def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvttpd2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttpd2dq (load addr:$src)))]>; // SSE2 instructions without OpSize prefix -def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>, TB, Requires<[HasSSE2]>; -def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src), +def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src), "cvtps2pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd (load addr:$src)))]>, TB, Requires<[HasSSE2]>; -def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>; -def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), +def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src), "cvtpd2ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2ps (load addr:$src)))]>; @@ -1396,33 +1398,33 @@ def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), // Aliases for intrinsics let isTwoAddress = 1 in { def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, GR32:$src2), + (outs VR128:$dst), (ins VR128:$src1, GR32:$src2), "cvtsi2sd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, GR32:$src2))]>; def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i32mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2), "cvtsi2sd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, (loadi32 addr:$src2)))]>; def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "cvtsd2ss {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))]>; def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), "cvtsd2ss {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1, (load addr:$src2)))]>; def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "cvtss2sd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))]>, XS, Requires<[HasSSE2]>; def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f32mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2), "cvtss2sd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, (load addr:$src2)))]>, XS, @@ -1449,50 +1451,50 @@ multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr, Intrinsic V2F64Int, bit Commutable = 0> { // Scalar operation, reg. - def SDr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src), + def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"), [(set FR64:$dst, (OpNode FR64:$src))]> { let isCommutable = Commutable; } // Scalar operation, mem. - def SDm : SDI<opc, MRMSrcMem, (ops FR64:$dst, f64mem:$src), + def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src), !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"), [(set FR64:$dst, (OpNode (load addr:$src)))]>; // Vector operation, reg. - def PDr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src), + def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"), [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> { let isCommutable = Commutable; } // Vector operation, mem. - def PDm : PDI<opc, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"), [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>; // Intrinsic operation, reg. - def SDr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src), + def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"), [(set VR128:$dst, (F64Int VR128:$src))]> { let isCommutable = Commutable; } // Intrinsic operation, mem. - def SDm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, sdmem:$src), + def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src), !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"), [(set VR128:$dst, (F64Int sse_load_f64:$src))]>; // Vector intrinsic operation, reg - def PDr_Int : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src), + def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"), [(set VR128:$dst, (V2F64Int VR128:$src))]> { let isCommutable = Commutable; } // Vector intrinsic operation, mem - def PDm_Int : PDI<opc, MRMSrcMem, (ops VR128:$dst, f64mem:$src), + def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"), [(set VR128:$dst, (V2F64Int (load addr:$src)))]>; } @@ -1507,19 +1509,19 @@ defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt, let isTwoAddress = 1 in { let isCommutable = 1 in { def ANDPDrr : PDI<0x54, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "andpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (and (bc_v2i64 (v2f64 VR128:$src1)), (bc_v2i64 (v2f64 VR128:$src2))))]>; def ORPDrr : PDI<0x56, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "orpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (or (bc_v2i64 (v2f64 VR128:$src1)), (bc_v2i64 (v2f64 VR128:$src2))))]>; def XORPDrr : PDI<0x57, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "xorpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (xor (bc_v2i64 (v2f64 VR128:$src1)), @@ -1527,31 +1529,31 @@ let isTwoAddress = 1 in { } def ANDPDrm : PDI<0x54, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "andpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (and (bc_v2i64 (v2f64 VR128:$src1)), (bc_v2i64 (memopv2f64 addr:$src2))))]>; def ORPDrm : PDI<0x56, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "orpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (or (bc_v2i64 (v2f64 VR128:$src1)), (bc_v2i64 (memopv2f64 addr:$src2))))]>; def XORPDrm : PDI<0x57, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "xorpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (xor (bc_v2i64 (v2f64 VR128:$src1)), (bc_v2i64 (memopv2f64 addr:$src2))))]>; def ANDNPDrr : PDI<0x55, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "andnpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))), (bc_v2i64 (v2f64 VR128:$src2))))]>; def ANDNPDrm : PDI<0x55, MRMSrcMem, - (ops VR128:$dst, VR128:$src1,f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2), "andnpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))), @@ -1560,12 +1562,12 @@ let isTwoAddress = 1 in { let isTwoAddress = 1 in { def CMPPDrri : PDIi8<0xC2, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, VR128:$src, imm:$cc))]>; def CMPPDrmi : PDIi8<0xC2, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), "cmp${cc}pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, (load addr:$src), imm:$cc))]>; @@ -1574,13 +1576,13 @@ let isTwoAddress = 1 in { // Shuffle and unpack instructions let isTwoAddress = 1 in { def SHUFPDrri : PDIi8<0xC6, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$src3)))]>; def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2, i8imm:$src3), "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, @@ -1590,14 +1592,14 @@ let isTwoAddress = 1 in { let AddedComplexity = 10 in { def UNPCKHPDrr : PDI<0x15, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "unpckhpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKH_shuffle_mask)))]>; def UNPCKHPDrm : PDI<0x15, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "unpckhpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle @@ -1605,14 +1607,14 @@ let isTwoAddress = 1 in { UNPCKH_shuffle_mask)))]>; def UNPCKLPDrr : PDI<0x14, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "unpcklpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKL_shuffle_mask)))]>; def UNPCKLPDrm : PDI<0x14, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "unpcklpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle @@ -1626,29 +1628,29 @@ let isTwoAddress = 1 in { // SSE integer instructions // Move Instructions -def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movdqa {$src, $dst|$dst, $src}", []>; -def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), +def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqa {$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv2i64 addr:$src))]>; -def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), +def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movdqa {$src, $dst|$dst, $src}", [(alignedstore (v2i64 VR128:$src), addr:$dst)]>; -def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), +def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqu {$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv2i64 addr:$src))]>, XS, Requires<[HasSSE2]>; -def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), +def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movdqu {$src, $dst|$dst, $src}", [(store (v2i64 VR128:$src), addr:$dst)]>, XS, Requires<[HasSSE2]>; // Intrinsic forms of MOVDQU load and store -def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), +def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqu {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, XS, Requires<[HasSSE2]>; -def MOVDQUmr_Int : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), +def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movdqu {$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, XS, Requires<[HasSSE2]>; @@ -1657,12 +1659,12 @@ let isTwoAddress = 1 in { multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, bit Commutable = 0> { - def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } - def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>; @@ -1670,14 +1672,14 @@ multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, string OpcodeStr, Intrinsic IntId> { - def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>; - def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>; - def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, (scalar_to_vector (i32 imm:$src2))))]>; @@ -1687,12 +1689,12 @@ multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, /// PDI_binop_rm - Simple SSE2 binary operator. multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, ValueType OpVT, bit Commutable = 0> { - def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> { let isCommutable = Commutable; } - def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpVT (OpNode VR128:$src1, (bitconvert (memopv2i64 addr:$src2)))))]>; @@ -1705,12 +1707,12 @@ multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, /// multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> { let isCommutable = Commutable; } - def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>; } @@ -1773,10 +1775,10 @@ defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>; // 128-bit logical shifts. let isTwoAddress = 1 in { def PSLLDQri : PDIi8<0x73, MRM7r, - (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), "pslldq {$src2, $dst|$dst, $src2}", []>; def PSRLDQri : PDIi8<0x73, MRM3r, - (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), "psrldq {$src2, $dst|$dst, $src2}", []>; // PSRADQri doesn't exist in SSE[1-3]. } @@ -1797,13 +1799,13 @@ defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>; let isTwoAddress = 1 in { def PANDNrr : PDI<0xDF, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "pandn {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1), VR128:$src2)))]>; def PANDNrm : PDI<0xDF, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "pandn {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1), (load addr:$src2))))]>; @@ -1824,13 +1826,13 @@ defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>; // Shuffle and unpack instructions def PSHUFDri : PDIi8<0x70, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i8imm:$src2), + (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle VR128:$src1, (undef), PSHUFD_shuffle_mask:$src2)))]>; def PSHUFDmi : PDIi8<0x70, MRMSrcMem, - (ops VR128:$dst, i128mem:$src1, i8imm:$src2), + (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle (bc_v4i32(memopv2i64 addr:$src1)), @@ -1839,14 +1841,14 @@ def PSHUFDmi : PDIi8<0x70, MRMSrcMem, // SSE2 with ImmT == Imm8 and XS prefix. def PSHUFHWri : Ii8<0x70, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i8imm:$src2), + (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (undef), PSHUFHW_shuffle_mask:$src2)))]>, XS, Requires<[HasSSE2]>; def PSHUFHWmi : Ii8<0x70, MRMSrcMem, - (ops VR128:$dst, i128mem:$src1, i8imm:$src2), + (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle (bc_v8i16 (memopv2i64 addr:$src1)), @@ -1856,14 +1858,14 @@ def PSHUFHWmi : Ii8<0x70, MRMSrcMem, // SSE2 with ImmT == Imm8 and XD prefix. def PSHUFLWri : Ii8<0x70, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (undef), PSHUFLW_shuffle_mask:$src2)))]>, XD, Requires<[HasSSE2]>; def PSHUFLWmi : Ii8<0x70, MRMSrcMem, - (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2), + (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle (bc_v8i16 (memopv2i64 addr:$src1)), @@ -1874,52 +1876,52 @@ def PSHUFLWmi : Ii8<0x70, MRMSrcMem, let isTwoAddress = 1 in { def PUNPCKLBWrr : PDI<0x60, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpcklbw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKL_shuffle_mask)))]>; def PUNPCKLBWrm : PDI<0x60, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpcklbw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (vector_shuffle VR128:$src1, (bc_v16i8 (memopv2i64 addr:$src2)), UNPCKL_shuffle_mask)))]>; def PUNPCKLWDrr : PDI<0x61, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpcklwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKL_shuffle_mask)))]>; def PUNPCKLWDrm : PDI<0x61, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpcklwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (bc_v8i16 (memopv2i64 addr:$src2)), UNPCKL_shuffle_mask)))]>; def PUNPCKLDQrr : PDI<0x62, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpckldq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKL_shuffle_mask)))]>; def PUNPCKLDQrm : PDI<0x62, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpckldq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)), UNPCKL_shuffle_mask)))]>; def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpcklqdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKL_shuffle_mask)))]>; def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpcklqdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (vector_shuffle VR128:$src1, @@ -1927,52 +1929,52 @@ let isTwoAddress = 1 in { UNPCKL_shuffle_mask)))]>; def PUNPCKHBWrr : PDI<0x68, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpckhbw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKH_shuffle_mask)))]>; def PUNPCKHBWrm : PDI<0x68, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpckhbw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (vector_shuffle VR128:$src1, (bc_v16i8 (memopv2i64 addr:$src2)), UNPCKH_shuffle_mask)))]>; def PUNPCKHWDrr : PDI<0x69, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpckhwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKH_shuffle_mask)))]>; def PUNPCKHWDrm : PDI<0x69, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpckhwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (bc_v8i16 (memopv2i64 addr:$src2)), UNPCKH_shuffle_mask)))]>; def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpckhdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKH_shuffle_mask)))]>; def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpckhdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)), UNPCKH_shuffle_mask)))]>; def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpckhqdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (vector_shuffle VR128:$src1, VR128:$src2, UNPCKH_shuffle_mask)))]>; def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpckhqdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (vector_shuffle VR128:$src1, @@ -1982,20 +1984,20 @@ let isTwoAddress = 1 in { // Extract / Insert def PEXTRWri : PDIi8<0xC5, MRMSrcReg, - (ops GR32:$dst, VR128:$src1, i32i8imm:$src2), + (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), (iPTR imm:$src2)))]>; let isTwoAddress = 1 in { def PINSRWrri : PDIi8<0xC4, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, + (outs VR128:$dst), (ins VR128:$src1, GR32:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1), GR32:$src2, (iPTR imm:$src3))))]>; def PINSRWrmi : PDIi8<0xC4, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, + (outs VR128:$dst), (ins VR128:$src1, i16mem:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, @@ -2005,81 +2007,81 @@ let isTwoAddress = 1 in { } // Mask creation -def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src), +def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), "pmovmskb {$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>; // Conditional store -def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask), +def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), "maskmovdqu {$mask, $src|$src, $mask}", [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, Imp<[EDI],[]>; // Non-temporal stores -def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), +def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movntpd {$src, $dst|$dst, $src}", [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>; -def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), "movntdq {$src, $dst|$dst, $src}", [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>; -def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src), +def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "movnti {$src, $dst|$dst, $src}", [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>, TB, Requires<[HasSSE2]>; // Flush cache -def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src), +def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflush $src", [(int_x86_sse2_clflush addr:$src)]>, TB, Requires<[HasSSE2]>; // Load, store, and memory fence -def LFENCE : I<0xAE, MRM5m, (ops), +def LFENCE : I<0xAE, MRM5m, (outs), (ins), "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>; -def MFENCE : I<0xAE, MRM6m, (ops), +def MFENCE : I<0xAE, MRM6m, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>; // Alias instructions that map zero vector to pxor / xorp* for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. let isReMaterializable = 1 in - def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst), + def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "pcmpeqd $dst, $dst", [(set VR128:$dst, (v2f64 immAllOnesV))]>; // FR64 to 128-bit vector conversion. -def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src), +def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src), "movsd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (scalar_to_vector FR64:$src)))]>; -def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src), +def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), "movsd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>; -def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src), +def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (scalar_to_vector GR32:$src)))]>; -def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), +def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>; -def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (ops FR32:$dst, GR32:$src), +def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), "movd {$src, $dst|$dst, $src}", [(set FR32:$dst, (bitconvert GR32:$src))]>; -def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src), +def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), "movd {$src, $dst|$dst, $src}", [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>; // SSE2 instructions with XS prefix -def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "movq {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, Requires<[HasSSE2]>; -def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src), +def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), "movq {$src, $dst|$dst, $src}", [(store (i64 (vector_extract (v2i64 VR128:$src), (iPTR 0))), addr:$dst)]>; @@ -2089,27 +2091,27 @@ def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src), // like this: // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), // (f32 FR32:$src)>; -def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src), +def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src), "movsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (vector_extract (v2f64 VR128:$src), (iPTR 0)))]>; -def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src), +def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movsd {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), addr:$dst)]>; -def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src), +def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), "movd {$src, $dst|$dst, $src}", [(set GR32:$dst, (vector_extract (v4i32 VR128:$src), (iPTR 0)))]>; -def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src), +def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src), "movd {$src, $dst|$dst, $src}", [(store (i32 (vector_extract (v4i32 VR128:$src), (iPTR 0))), addr:$dst)]>; -def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src), +def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), "movd {$src, $dst|$dst, $src}", [(set GR32:$dst, (bitconvert FR32:$src))]>; -def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src), +def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src), "movd {$src, $dst|$dst, $src}", [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>; @@ -2118,12 +2120,12 @@ def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src), // Three operand (but two address) aliases. let isTwoAddress = 1 in { def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, FR64:$src2), + (outs VR128:$dst), (ins VR128:$src1, FR64:$src2), "movsd {$src2, $dst|$dst, $src2}", []>; let AddedComplexity = 15 in def MOVLPDrr : SDI<0x10, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "movsd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, VR128:$src2, @@ -2131,14 +2133,14 @@ let isTwoAddress = 1 in { } // Store / copy lower 64-bits of a XMM register. -def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src), +def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), "movq {$src, $dst|$dst, $src}", [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>; // Move to lower bits of a VR128 and zeroing upper bits. // Loading from memory automatically zeroing upper bits. let AddedComplexity = 20 in - def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src), + def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), "movsd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV, @@ -2148,14 +2150,14 @@ let AddedComplexity = 20 in let AddedComplexity = 15 in // movd / movq to XMM register zero-extends -def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src), +def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV, (v4i32 (scalar_to_vector GR32:$src)), MOVL_shuffle_mask)))]>; let AddedComplexity = 20 in -def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), +def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV, @@ -2164,12 +2166,12 @@ def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), // Moving from XMM to XMM but still clear upper 64 bits. let AddedComplexity = 15 in -def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>, XS, Requires<[HasSSE2]>; let AddedComplexity = 20 in -def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "movq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_movl_dq (bitconvert (memopv2i64 addr:$src))))]>, @@ -2186,42 +2188,42 @@ def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), // S3SI - SSE3 instructions with XS prefix. // S3DI - SSE3 instructions with XD prefix. -class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>; -class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>; -class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>; +class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>; +class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>; +class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>; // Move Instructions -def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movshdup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src, (undef), MOVSHDUP_shuffle_mask)))]>; -def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movshdup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle (memopv4f32 addr:$src), (undef), MOVSHDUP_shuffle_mask)))]>; -def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movsldup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src, (undef), MOVSLDUP_shuffle_mask)))]>; -def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movsldup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle (memopv4f32 addr:$src), (undef), MOVSLDUP_shuffle_mask)))]>; -def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src), +def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movddup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src, (undef), SSE_splat_lo_mask)))]>; -def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src), +def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), "movddup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (vector_shuffle @@ -2232,46 +2234,46 @@ def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src), // Arithmetic let isTwoAddress = 1 in { def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "addsubps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, VR128:$src2))]>; def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "addsubps {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, (load addr:$src2)))]>; def ADDSUBPDrr : S3I<0xD0, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "addsubpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1, VR128:$src2))]>; def ADDSUBPDrm : S3I<0xD0, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), "addsubpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1, (load addr:$src2)))]>; } -def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src), +def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "lddqu {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; // Horizontal ops class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId> - : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>; class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId> - : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), + : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>; class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId> - : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>; class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId> - : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), + : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>; @@ -2287,9 +2289,9 @@ let isTwoAddress = 1 in { } // Thread synchronization -def MONITOR : I<0xC8, RawFrm, (ops), "monitor", +def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor", [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>; -def MWAIT : I<0xC9, RawFrm, (ops), "mwait", +def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait", [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>; // vector_shuffle v1, <undef> <1, 1, 3, 3> @@ -2321,21 +2323,23 @@ let AddedComplexity = 20 in // SS38I - SSSE3 instructions with T8 and OpSize prefixes. // SS3AI - SSSE3 instructions with TA and OpSize prefixes. -class SS38I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>; -class SS3AI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>; +class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>; +class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>; /// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64. let isTwoAddress = 1 in { multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, bit Commutable = 0> { - def rr : SS38I<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> { let isCommutable = Commutable; } - def rm : SS38I<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (IntId VR128:$src1, diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td index ac4384631e..7479db4ea2 100644 --- a/lib/Target/X86/X86InstrX86-64.td +++ b/lib/Target/X86/X86InstrX86-64.td @@ -43,25 +43,31 @@ def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr", // Instruction templates... // -class RI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : I<o, F, ops, asm, pattern>, REX_W; -class RIi8 <bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii8<o, F, ops, asm, pattern>, REX_W; -class RIi32 <bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : Ii32<o, F, ops, asm, pattern>, REX_W; - -class RIi64<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> - : X86Inst<o, f, Imm64, ops, asm>, REX_W { +class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, REX_W; +class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, REX_W; +class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii32<o, F, outs, ins, asm, pattern>, REX_W; + +class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm, + list<dag> pattern> + : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W { let Pattern = pattern; let CodeSize = 3; } -class RSSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : SSI<o, F, ops, asm, pattern>, REX_W; -class RSDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : SDI<o, F, ops, asm, pattern>, REX_W; -class RPDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> - : PDI<o, F, ops, asm, pattern>, REX_W; +class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : SSI<o, F, outs, ins, asm, pattern>, REX_W; +class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : SDI<o, F, outs, ins, asm, pattern>, REX_W; +class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : PDI<o, F, outs, ins, asm, pattern>, REX_W; //===----------------------------------------------------------------------===// // Pattern fragments... @@ -104,7 +110,7 @@ def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; // Instruction list... // -def IMPLICIT_DEF_GR64 : I<0, Pseudo, (ops GR64:$dst), +def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins), "#IMPLICIT_DEF $dst", [(set GR64:$dst, (undef))]>; @@ -118,19 +124,19 @@ let isCall = 1, noResults = 1 in MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15] in { - def CALL64pcrel32 : I<0xE8, RawFrm, (ops i64imm:$dst, variable_ops), + def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops), "call ${dst:call}", []>; - def CALL64r : I<0xFF, MRM2r, (ops GR64:$dst, variable_ops), + def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops), "call {*}$dst", [(X86call GR64:$dst)]>; - def CALL64m : I<0xFF, MRM2m, (ops i64mem:$dst, variable_ops), + def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops), "call {*}$dst", []>; } // Branches let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in { - def JMP64r : I<0xFF, MRM4r, (ops GR64:$dst), "jmp{q} {*}$dst", + def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q} {*}$dst", [(brind GR64:$dst)]>; - def JMP64m : I<0xFF, MRM4m, (ops i64mem:$dst), "jmp{q} {*}$dst", + def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q} {*}$dst", [(brind (loadi64 addr:$dst))]>; } @@ -138,38 +144,38 @@ let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in { // Miscellaneous Instructions... // def LEAVE64 : I<0xC9, RawFrm, - (ops), "leave", []>, Imp<[RBP,RSP],[RBP,RSP]>; + (outs), (ins), "leave", []>, Imp<[RBP,RSP],[RBP,RSP]>; def POP64r : I<0x58, AddRegFrm, - (ops GR64:$reg), "pop{q} $reg", []>, Imp<[RSP],[RSP]>; + (outs GR64:$reg), (ins), "pop{q} $reg", []>, Imp<[RSP],[RSP]>; def PUSH64r : I<0x50, AddRegFrm, - (ops GR64:$reg), "push{q} $reg", []>, Imp<[RSP],[RSP]>; + (outs), (ins GR64:$reg), "push{q} $reg", []>, Imp<[RSP],[RSP]>; def LEA64_32r : I<0x8D, MRMSrcMem, - (ops GR32:$dst, lea64_32mem:$src), + (outs GR32:$dst), (ins lea64_32mem:$src), "lea{l} {$src|$dst}, {$dst|$src}", [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>; -def LEA64r : RI<0x8D, MRMSrcMem, (ops GR64:$dst, lea64mem:$src), +def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), "lea{q} {$src|$dst}, {$dst|$src}", [(set GR64:$dst, lea64addr:$src)]>; let isTwoAddress = 1 in -def BSWAP64r : RI<0xC8, AddRegFrm, (ops GR64:$dst, GR64:$src), +def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), "bswap{q} $dst", [(set GR64:$dst, (bswap GR64:$src))]>, TB; // Exchange -def XCHG64rr : RI<0x87, MRMDestReg, (ops GR64:$src1, GR64:$src2), +def XCHG64rr : RI<0x87, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), "xchg{q} {$src2|$src1}, {$src1|$src2}", []>; -def XCHG64mr : RI<0x87, MRMDestMem, (ops i64mem:$src1, GR64:$src2), +def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), "xchg{q} {$src2|$src1}, {$src1|$src2}", []>; -def XCHG64rm : RI<0x87, MRMSrcMem, (ops GR64:$src1, i64mem:$src2), +def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), "xchg{q} {$src2|$src1}, {$src1|$src2}", []>; // Repeat string ops -def REP_MOVSQ : RI<0xA5, RawFrm, (ops), "{rep;movsq|rep movsq}", +def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", [(X86rep_movs i64)]>, Imp<[RCX,RDI,RSI], [RCX,RDI,RSI]>, REP; -def REP_STOSQ : RI<0xAB, RawFrm, (ops), "{rep;stosq|rep stosq}", +def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", [(X86rep_stos i64)]>, Imp<[RAX,RCX,RDI], [RCX,RDI]>, REP; @@ -177,65 +183,65 @@ def REP_STOSQ : RI<0xAB, RawFrm, (ops), "{rep;stosq|rep stosq}", // Move Instructions... // -def MOV64rr : RI<0x89, MRMDestReg, (ops GR64:$dst, GR64:$src), +def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), "mov{q} {$src, $dst|$dst, $src}", []>; -def MOV64ri : RIi64<0xB8, AddRegFrm, (ops GR64:$dst, i64imm:$src), +def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), "movabs{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, imm:$src)]>; -def MOV64ri32 : RIi32<0xC7, MRM0r, (ops GR64:$dst, i64i32imm:$src), +def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), "mov{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, i64immSExt32:$src)]>; -def MOV64rm : RI<0x8B, MRMSrcMem, (ops GR64:$dst, i64mem:$src), +def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "mov{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (load addr:$src))]>; -def MOV64mr : RI<0x89, MRMDestMem, (ops i64mem:$dst, GR64:$src), +def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "mov{q} {$src, $dst|$dst, $src}", [(store GR64:$src, addr:$dst)]>; -def MOV64mi32 : RIi32<0xC7, MRM0m, (ops i64mem:$dst, i64i32imm:$src), +def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), "mov{q} {$src, $dst|$dst, $src}", [(store i64immSExt32:$src, addr:$dst)]>; // Sign/Zero extenders -def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (ops GR64:$dst, GR8 :$src), +def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), "movs{bq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (sext GR8:$src))]>, TB; -def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (ops GR64:$dst, i8mem :$src), +def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), "movs{bq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB; -def MOVSX64rr16: RI<0xBF, MRMSrcReg, (ops GR64:$dst, GR16:$src), +def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), "movs{wq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (sext GR16:$src))]>, TB; -def MOVSX64rm16: RI<0xBF, MRMSrcMem, (ops GR64:$dst, i16mem:$src), +def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), "movs{wq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB; -def MOVSX64rr32: RI<0x63, MRMSrcReg, (ops GR64:$dst, GR32:$src), +def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), "movs{lq|xd} {$src, $dst|$dst, $src}", [(set GR64:$dst, (sext GR32:$src))]>; -def MOVSX64rm32: RI<0x63, MRMSrcMem, (ops GR64:$dst, i32mem:$src), +def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), "movs{lq|xd} {$src, $dst|$dst, $src}", [(set GR64:$dst, (sextloadi64i32 addr:$src))]>; -def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (ops GR64:$dst, GR8 :$src), +def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), "movz{bq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (zext GR8:$src))]>, TB; -def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (ops GR64:$dst, i8mem :$src), +def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), "movz{bq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB; -def MOVZX64rr16: RI<0xB7, MRMSrcReg, (ops GR64:$dst, GR16:$src), +def MOVZX64rr16: RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), "movz{wq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (zext GR16:$src))]>, TB; -def MOVZX64rm16: RI<0xB7, MRMSrcMem, (ops GR64:$dst, i16mem:$src), +def MOVZX64rm16: RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), "movz{wq|x} {$src, $dst|$dst, $src}", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB; -def CDQE : RI<0x98, RawFrm, (ops), +def CDQE : RI<0x98, RawFrm, (outs), (ins), "{cltq|cdqe}", []>, Imp<[EAX],[RAX]>; // RAX = signext(EAX) -def CQO : RI<0x99, RawFrm, (ops), +def CQO : RI<0x99, RawFrm, (outs), (ins), "{cqto|cqo}", []>, Imp<[RAX],[RAX,RDX]>; // RDX:RAX = signext(RAX) //===----------------------------------------------------------------------===// @@ -245,205 +251,205 @@ def CQO : RI<0x99, RawFrm, (ops), let isTwoAddress = 1 in { let isConvertibleToThreeAddress = 1 in { let isCommutable = 1 in -def ADD64rr : RI<0x01, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "add{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>; -def ADD64ri32 : RIi32<0x81, MRM0r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), +def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "add{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>; -def ADD64ri8 : RIi8<0x83, MRM0r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), +def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "add{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>; } // isConvertibleToThreeAddress -def ADD64rm : RI<0x03, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "add{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>; } // isTwoAddress -def ADD64mr : RI<0x01, MRMDestMem, (ops i64mem:$dst, GR64:$src2), +def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "add{q} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>; -def ADD64mi32 : RIi32<0x81, MRM0m, (ops i64mem:$dst, i64i32imm :$src2), +def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2), "add{q} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; -def ADD64mi8 : RIi8<0x83, MRM0m, (ops i64mem:$dst, i64i8imm :$src2), +def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "add{q} {$src2, $dst|$dst, $src2}", [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; let isTwoAddress = 1 in { let isCommutable = 1 in -def ADC64rr : RI<0x11, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; -def ADC64rm : RI<0x13, MRMSrcMem , (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>; -def ADC64ri32 : RIi32<0x81, MRM2r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>; -def ADC64ri8 : RIi8<0x83, MRM2r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>; } // isTwoAddress -def ADC64mr : RI<0x11, MRMDestMem, (ops i64mem:$dst, GR64:$src2), +def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>; -def ADC64mi32 : RIi32<0x81, MRM2m, (ops i64mem:$dst, i64i32imm:$src2), +def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; -def ADC64mi8 : RIi8<0x83, MRM2m, (ops i64mem:$dst, i64i8imm :$src2), +def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "adc{q} {$src2, $dst|$dst, $src2}", [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; let isTwoAddress = 1 in { -def SUB64rr : RI<0x29, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>; -def SUB64rm : RI<0x2B, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>; -def SUB64ri32 : RIi32<0x81, MRM5r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), +def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>; -def SUB64ri8 : RIi8<0x83, MRM5r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), +def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>; } // isTwoAddress -def SUB64mr : RI<0x29, MRMDestMem, (ops i64mem:$dst, GR64:$src2), +def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>; -def SUB64mi32 : RIi32<0x81, MRM5m, (ops i64mem:$dst, i64i32imm:$src2), +def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; -def SUB64mi8 : RIi8<0x83, MRM5m, (ops i64mem:$dst, i64i8imm :$src2), +def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "sub{q} {$src2, $dst|$dst, $src2}", [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; let isTwoAddress = 1 in { -def SBB64rr : RI<0x19, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>; -def SBB64rm : RI<0x1B, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>; -def SBB64ri32 : RIi32<0x81, MRM3r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>; -def SBB64ri8 : RIi8<0x83, MRM3r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>; } // isTwoAddress -def SBB64mr : RI<0x19, MRMDestMem, (ops i64mem:$dst, GR64:$src2), +def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>; -def SBB64mi32 : RIi32<0x81, MRM3m, (ops i64mem:$dst, i64i32imm:$src2), +def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; -def SBB64mi8 : RIi8<0x83, MRM3m, (ops i64mem:$dst, i64i8imm :$src2), +def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "sbb{q} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; // Unsigned multiplication -def MUL64r : RI<0xF7, MRM4r, (ops GR64:$src), +def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src), "mul{q} $src", []>, Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64 -def MUL64m : RI<0xF7, MRM4m, (ops i64mem:$src), +def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src), "mul{q} $src", []>, Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64] // Signed multiplication -def IMUL64r : RI<0xF7, MRM5r, (ops GR64:$src), +def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q} $src", []>, Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64 -def IMUL64m : RI<0xF7, MRM5m, (ops i64mem:$src), +def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src), "imul{q} $src", []>, Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64] let isTwoAddress = 1 in { let isCommutable = 1 in -def IMUL64rr : RI<0xAF, MRMSrcReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "imul{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB; -def IMUL64rm : RI<0xAF, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "imul{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB; } // isTwoAddress // Suprisingly enough, these are not two address instructions! def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32 - (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>; def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8 - (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>; def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32 - (ops GR64:$dst, i64mem:$src1, i64i32imm:$src2), + (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2), "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>; def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 - (ops GR64:$dst, i64mem:$src1, i64i8imm: $src2), + (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2), "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>; // Unsigned division / remainder -def DIV64r : RI<0xF7, MRM6r, (ops GR64:$src), // RDX:RAX/r64 = RAX,RDX +def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX "div{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>; -def DIV64m : RI<0xF7, MRM6m, (ops i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX +def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX "div{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>; // Signed division / remainder -def IDIV64r: RI<0xF7, MRM7r, (ops GR64:$src), // RDX:RAX/r64 = RAX,RDX +def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX "idiv{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>; -def IDIV64m: RI<0xF7, MRM7m, (ops i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX +def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX "idiv{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>; // Unary instructions let CodeSize = 2 in { let isTwoAddress = 1 in -def NEG64r : RI<0xF7, MRM3r, (ops GR64:$dst, GR64:$src), "neg{q} $dst", +def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q} $dst", [(set GR64:$dst, (ineg GR64:$src))]>; -def NEG64m : RI<0xF7, MRM3m, (ops i64mem:$dst), "neg{q} $dst", +def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q} $dst", [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>; let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in -def INC64r : RI<0xFF, MRM0r, (ops GR64:$dst, GR64:$src), "inc{q} $dst", +def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q} $dst", [(set GR64:$dst, (add GR64:$src, 1))]>; -def INC64m : RI<0xFF, MRM0m, (ops i64mem:$dst), "inc{q} $dst", +def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q} $dst", [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>; let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in -def DEC64r : RI<0xFF, MRM1r, (ops GR64:$dst, GR64:$src), "dec{q} $dst", +def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q} $dst", [(set GR64:$dst, (add GR64:$src, -1))]>; -def DEC64m : RI<0xFF, MRM1m, (ops i64mem:$dst), "dec{q} $dst", +def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q} $dst", [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>; // In 64-bit mode, single byte INC and DEC cannot be encoded. let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def INC64_16r : I<0xFF, MRM0r, (ops GR16:$dst, GR16:$src), "inc{w} $dst", +def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w} $dst", [(set GR16:$dst, (add GR16:$src, 1))]>, OpSize, Requires<[In64BitMode]>; -def INC64_32r : I<0xFF, MRM0r, (ops GR32:$dst, GR32:$src), "inc{l} $dst", +def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l} $dst", [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In64BitMode]>; -def DEC64_16r : I<0xFF, MRM1r, (ops GR16:$dst, GR16:$src), "dec{w} $dst", +def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w} $dst", [(set GR16:$dst, (add GR16:$src, -1))]>, OpSize, Requires<[In64BitMode]>; -def DEC64_32r : I<0xFF, MRM1r, (ops GR32:$dst, GR32:$src), "dec{l} $dst", +def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l} $dst", [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In64BitMode]>; } // isConvertibleToThreeAddress @@ -452,138 +458,138 @@ def DEC64_32r : I<0xFF, MRM1r, (ops GR32:$dst, GR32:$src), "dec{l} $dst", // Shift instructions let isTwoAddress = 1 in { -def SHL64rCL : RI<0xD3, MRM4r, (ops GR64:$dst, GR64:$src), +def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src), "shl{q} {%cl, $dst|$dst, %CL}", [(set GR64:$dst, (shl GR64:$src, CL))]>, Imp<[CL],[]>; -def SHL64ri : RIi8<0xC1, MRM4r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), +def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "shl{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; -def SHL64r1 : RI<0xD1, MRM4r, (ops GR64:$dst, GR64:$src1), +def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), "shl{q} $dst", []>; } // isTwoAddress -def SHL64mCL : RI<0xD3, MRM4m, (ops i64mem:$dst), +def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), "shl{q} {%cl, $dst|$dst, %CL}", [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; -def SHL64mi : RIi8<0xC1, MRM4m, (ops i64mem:$dst, i8imm:$src), +def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src), "shl{q} {$src, $dst|$dst, $src}", [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SHL64m1 : RI<0xD1, MRM4m, (ops i64mem:$dst), +def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), "shl{q} $dst", [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; let isTwoAddress = 1 in { -def SHR64rCL : RI<0xD3, MRM5r, (ops GR64:$dst, GR64:$src), +def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src), "shr{q} {%cl, $dst|$dst, %CL}", [(set GR64:$dst, (srl GR64:$src, CL))]>, Imp<[CL],[]>; -def SHR64ri : RIi8<0xC1, MRM5r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), +def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "shr{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; -def SHR64r1 : RI<0xD1, MRM5r, (ops GR64:$dst, GR64:$src1), +def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), "shr{q} $dst", [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>; } // isTwoAddress -def SHR64mCL : RI<0xD3, MRM5m, (ops i64mem:$dst), +def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), "shr{q} {%cl, $dst|$dst, %CL}", [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; -def SHR64mi : RIi8<0xC1, MRM5m, (ops i64mem:$dst, i8imm:$src), +def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src), "shr{q} {$src, $dst|$dst, $src}", [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SHR64m1 : RI<0xD1, MRM5m, (ops i64mem:$dst), +def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), "shr{q} $dst", [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; let isTwoAddress = 1 in { -def SAR64rCL : RI<0xD3, MRM7r, (ops GR64:$dst, GR64:$src), +def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src), "sar{q} {%cl, $dst|$dst, %CL}", [(set GR64:$dst, (sra GR64:$src, CL))]>, Imp<[CL],[]>; -def SAR64ri : RIi8<0xC1, MRM7r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), +def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "sar{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>; -def SAR64r1 : RI<0xD1, MRM7r, (ops GR64:$dst, GR64:$src1), +def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), "sar{q} $dst", [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>; } // isTwoAddress -def SAR64mCL : RI<0xD3, MRM7m, (ops i64mem:$dst), +def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), "sar{q} {%cl, $dst|$dst, %CL}", [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; -def SAR64mi : RIi8<0xC1, MRM7m, (ops i64mem:$dst, i8imm:$src), +def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src), "sar{q} {$src, $dst|$dst, $src}", [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SAR64m1 : RI<0xD1, MRM7m, (ops i64mem:$dst), +def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), "sar{q} $dst", [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; // Rotate instructions let isTwoAddress = 1 in { -def ROL64rCL : RI<0xD3, MRM0r, (ops GR64:$dst, GR64:$src), +def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src), "rol{q} {%cl, $dst|$dst, %CL}", [(set GR64:$dst, (rotl GR64:$src, CL))]>, Imp<[CL],[]>; -def ROL64ri : RIi8<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), +def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "rol{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; -def ROL64r1 : RI<0xD1, MRM0r, (ops GR64:$dst, GR64:$src1), +def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "rol{q} $dst", [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; } // isTwoAddress -def ROL64mCL : I<0xD3, MRM0m, (ops i64mem:$dst), +def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst), "rol{q} {%cl, $dst|$dst, %CL}", [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; -def ROL64mi : RIi8<0xC1, MRM0m, (ops i64mem:$dst, i8imm:$src), +def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src), "rol{q} {$src, $dst|$dst, $src}", [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def ROL64m1 : RI<0xD1, MRM0m, (ops i64mem:$dst), +def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), "rol{q} $dst", [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; let isTwoAddress = 1 in { -def ROR64rCL : RI<0xD3, MRM1r, (ops GR64:$dst, GR64:$src), +def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src), "ror{q} {%cl, $dst|$dst, %CL}", [(set GR64:$dst, (rotr GR64:$src, CL))]>, Imp<[CL],[]>; -def ROR64ri : RIi8<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), +def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "ror{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>; -def ROR64r1 : RI<0xD1, MRM1r, (ops GR64:$dst, GR64:$src1), +def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "ror{q} $dst", [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>; } // isTwoAddress -def ROR64mCL : RI<0xD3, MRM1m, (ops i64mem:$dst), +def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), "ror{q} {%cl, $dst|$dst, %CL}", [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>, Imp<[CL],[]>; -def ROR64mi : RIi8<0xC1, MRM1m, (ops i64mem:$dst, i8imm:$src), +def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src), "ror{q} {$src, $dst|$dst, $src}", [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def ROR64m1 : RI<0xD1, MRM1m, (ops i64mem:$dst), +def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), "ror{q} $dst", [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; // Double shift instructions (generalizations of rotate) let isTwoAddress = 1 in { -def SHLD64rrCL : RI<0xA5, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; -def SHRD64rrCL : RI<0xAD, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "shrd{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction def SHLD64rri8 : RIi8<0xA4, MRMDestReg, - (ops GR64:$dst, GR64:$src1, GR64:$src2, i8imm:$src3), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3), "shld{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; def SHRD64rri8 : RIi8<0xAC, MRMDestReg, - (ops GR64:$dst, GR64:$src1, GR64:$src2, i8imm:$src3), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3), "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; } // isCommutable @@ -592,18 +598,18 @@ def SHRD64rri8 : RIi8<0xAC, MRMDestReg, // Temporary hack: there is no patterns associated with these instructions // so we have to tell tblgen that these do not produce results. let noResults = 1 in { -def SHLD64mrCL : RI<0xA5, MRMDestMem, (ops i64mem:$dst, GR64:$src2), +def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; -def SHRD64mrCL : RI<0xAD, MRMDestMem, (ops i64mem:$dst, GR64:$src2), +def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "shrd{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; def SHLD64mri8 : RIi8<0xA4, MRMDestMem, - (ops i64mem:$dst, GR64:$src2, i8imm:$src3), + (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), "shld{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; def SHRD64mri8 : RIi8<0xAC, MRMDestMem, - (ops i64mem:$dst, GR64:$src2, i8imm:$src3), + (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB; } // noResults @@ -613,94 +619,94 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem, // let isTwoAddress = 1 in -def NOT64r : RI<0xF7, MRM2r, (ops GR64:$dst, GR64:$src), "not{q} $dst", +def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q} $dst", [(set GR64:$dst, (not GR64:$src))]>; -def NOT64m : RI<0xF7, MRM2m, (ops i64mem:$dst), "not{q} $dst", +def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q} $dst", [(store (not (loadi64 addr:$dst)), addr:$dst)]>; let isTwoAddress = 1 in { let isCommutable = 1 in def AND64rr : RI<0x21, MRMDestReg, - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "and{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; def AND64rm : RI<0x23, MRMSrcMem, - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "and{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>; def AND64ri32 : RIi32<0x81, MRM4r, - (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "and{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>; def AND64ri8 : RIi8<0x83, MRM4r, - (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "and{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>; } // isTwoAddress def AND64mr : RI<0x21, MRMDestMem, - (ops i64mem:$dst, GR64:$src), + (outs), (ins i64mem:$dst, GR64:$src), "and{q} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>; def AND64mi32 : RIi32<0x81, MRM4m, - (ops i64mem:$dst, i64i32imm:$src), + (outs), (ins i64mem:$dst, i64i32imm:$src), "and{q} {$src, $dst|$dst, $src}", [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>; def AND64mi8 : RIi8<0x83, MRM4m, - (ops i64mem:$dst, i64i8imm :$src), + (outs), (ins i64mem:$dst, i64i8imm :$src), "and{q} {$src, $dst|$dst, $src}", [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; let isTwoAddress = 1 in { let isCommutable = 1 in -def OR64rr : RI<0x09, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "or{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; -def OR64rm : RI<0x0B, MRMSrcMem , (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "or{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>; -def OR64ri32 : RIi32<0x81, MRM1r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), +def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "or{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>; -def OR64ri8 : RIi8<0x83, MRM1r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), +def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "or{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>; } // isTwoAddress -def OR64mr : RI<0x09, MRMDestMem, (ops i64mem:$dst, GR64:$src), +def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "or{q} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>; -def OR64mi32 : RIi32<0x81, MRM1m, (ops i64mem:$dst, i64i32imm:$src), +def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src), "or{q} {$src, $dst|$dst, $src}", [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>; -def OR64mi8 : RIi8<0x83, MRM1m, (ops i64mem:$dst, i64i8imm:$src), +def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src), "or{q} {$src, $dst|$dst, $src}", [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; let isTwoAddress = 1 in { let isCommutable = 1 in -def XOR64rr : RI<0x31, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2), +def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "xor{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; -def XOR64rm : RI<0x33, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2), +def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "xor{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>; def XOR64ri32 : RIi32<0x81, MRM6r, - (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "xor{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>; -def XOR64ri8 : RIi8<0x83, MRM6r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2), +def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "xor{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>; } // isTwoAddress -def XOR64mr : RI<0x31, MRMDestMem, (ops i64mem:$dst, GR64:$src), +def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "xor{q} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>; -def XOR64mi32 : RIi32<0x81, MRM6m, (ops i64mem:$dst, i64i32imm:$src), +def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src), "xor{q} {$src, $dst|$dst, $src}", [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>; -def XOR64mi8 : RIi8<0x83, MRM6m, (ops i64mem:$dst, i64i8imm :$src), +def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src), "xor{q} {$src, $dst|$dst, $src}", [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; @@ -710,180 +716,180 @@ def XOR64mi8 : RIi8<0x83, MRM6m, (ops i64mem:$dst, i64i8imm :$src), // Integer comparison let isCommutable = 1 in -def TEST64rr : RI<0x85, MRMDestReg, (ops GR64:$src1, GR64:$src2), +def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), "test{q} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>; -def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2), +def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), "test{q} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>; -def TEST64ri32 : RIi32<0xF7, MRM0r, (ops GR64:$src1, i64i32imm:$src2), +def TEST64ri32 : RIi32<0xF7, MRM0r, (outs), (ins GR64:$src1, i64i32imm:$src2), "test{q} {$src2, $src1|$src1, $src2}", [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>; -def TEST64mi32 : RIi32<0xF7, MRM0m, (ops i64mem:$src1, i64i32imm:$src2), +def TEST64mi32 : RIi32<0xF7, MRM0m, (outs), (ins i64mem:$src1, i64i32imm:$src2), "test{q} {$src2, $src1|$src1, $src2}", [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>; -def CMP64rr : RI<0x39, MRMDestReg, (ops GR64:$src1, GR64:$src2), +def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp GR64:$src1, GR64:$src2)]>; -def CMP64mr : RI<0x39, MRMDestMem, (ops i64mem:$src1, GR64:$src2), +def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi64 addr:$src1), GR64:$src2)]>; -def CMP64rm : RI<0x3B, MRMSrcMem, (ops GR64:$src1, i64mem:$src2), +def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp GR64:$src1, (loadi64 addr:$src2))]>; -def CMP64ri32 : RIi32<0x81, MRM7r, (ops GR64:$src1, i64i32imm:$src2), +def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp GR64:$src1, i64immSExt32:$src2)]>; -def CMP64mi32 : RIi32<0x81, MRM7m, (ops i64mem:$src1, i64i32imm:$src2), +def CMP64mi32 : RIi32<0x81, MRM7m, (outs), (ins i64mem:$src1, i64i32imm:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2)]>; -def CMP64mi8 : RIi8<0x83, MRM7m, (ops i64mem:$src1, i64i8imm:$src2), +def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2)]>; -def CMP64ri8 : RIi8<0x83, MRM7r, (ops GR64:$src1, i64i8imm:$src2), +def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), "cmp{q} {$src2, $src1|$src1, $src2}", [(X86cmp GR64:$src1, i64immSExt8:$src2)]>; // Conditional moves let isTwoAddress = 1 in { def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovb {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_B))]>, TB; def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovb {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_B))]>, TB; def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovae {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_AE))]>, TB; def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovae {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_AE))]>, TB; def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmove {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_E))]>, TB; def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmove {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_E))]>, TB; def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovne {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_NE))]>, TB; def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovne {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_NE))]>, TB; def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovbe {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_BE))]>, TB; def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovbe {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_BE))]>, TB; def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmova {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_A))]>, TB; def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmova {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_A))]>, TB; def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovl {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_L))]>, TB; def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovl {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_L))]>, TB; def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovge {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_GE))]>, TB; def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovge {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_GE))]>, TB; def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovle {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_LE))]>, TB; def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovle {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_LE))]>, TB; def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovg {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_G))]>, TB; def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovg {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_G))]>, TB; def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovs {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_S))]>, TB; def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovs {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_S))]>, TB; def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovns {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_NS))]>, TB; def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovns {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_NS))]>, TB; def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovp {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_P))]>, TB; def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovp {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_P))]>, TB; def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64 - (ops GR64:$dst, GR64:$src1, GR64:$src2), + (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "cmovnp {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, X86_COND_NP))]>, TB; def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64] - (ops GR64:$dst, GR64:$src1, i64mem:$src2), + (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "cmovnp {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), X86_COND_NP))]>, TB; @@ -894,78 +900,78 @@ def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64] // // f64 -> signed i64 -def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (ops GR64:$dst, VR128:$src), +def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), "cvtsd2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic -def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (ops GR64:$dst, f128mem:$src), +def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src), "cvtsd2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic -def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (ops GR64:$dst, FR64:$src), +def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src), "cvttsd2si{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (fp_to_sint FR64:$src))]>; -def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (ops GR64:$dst, f64mem:$src), +def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src), "cvttsd2si{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>; -def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (ops GR64:$dst, VR128:$src), +def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), "cvttsd2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic -def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (ops GR64:$dst, f128mem:$src), +def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src), "cvttsd2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic // Signed i64 -> f64 -def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR64:$src), +def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), "cvtsi2sd{q} {$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp GR64:$src))]>; -def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (ops FR64:$dst, i64mem:$src), +def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), "cvtsi2sd{q} {$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>; let isTwoAddress = 1 in { def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, GR64:$src2), + (outs VR128:$dst), (ins VR128:$src1, GR64:$src2), "cvtsi2sd{q} {$src2, $dst|$dst, $src2}", []>; // TODO: add intrinsic def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2), "cvtsi2sd{q} {$src2, $dst|$dst, $src2}", []>; // TODO: add intrinsic } // isTwoAddress // Signed i64 -> f32 -def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR64:$src), +def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src), "cvtsi2ss{q} {$src, $dst|$dst, $src}", [(set FR32:$dst, (sint_to_fp GR64:$src))]>; -def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (ops FR32:$dst, i64mem:$src), +def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src), "cvtsi2ss{q} {$src, $dst|$dst, $src}", [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>; let isTwoAddress = 1 in { def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, GR64:$src2), + (outs VR128:$dst), (ins VR128:$src1, GR64:$src2), "cvtsi2ss{q} {$src2, $dst|$dst, $src2}", []>; // TODO: add intrinsic def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, i64mem:$src2), + (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2), "cvtsi2ss{q} {$src2, $dst|$dst, $src2}", []>; // TODO: add intrinsic } // isTwoAddress // f32 -> signed i64 -def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (ops GR64:$dst, VR128:$src), +def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), "cvtss2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic -def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (ops GR64:$dst, f32mem:$src), +def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src), "cvtss2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic -def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (ops GR64:$dst, FR32:$src), +def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src), "cvttss2si{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (fp_to_sint FR32:$src))]>; -def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src), +def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src), "cvttss2si{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>; -def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (ops GR64:$dst, VR128:$src), +def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), "cvttss2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic -def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src), +def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src), "cvttss2si{q} {$src, $dst|$dst, $src}", []>; // TODO: add intrinsic @@ -975,32 +981,32 @@ def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src), // Truncate // In 64-mode, each 64-bit and 32-bit registers has a low 8-bit sub-register. -def TRUNC_64to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR64:$src), +def TRUNC_64to8 : I<0x88, MRMDestReg, (outs GR8:$dst), (ins GR64:$src), "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", [(set GR8:$dst, (trunc GR64:$src))]>; -def TRUNC_32to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32:$src), +def TRUNC_32to8 : I<0x88, MRMDestReg, (outs GR8:$dst), (ins GR32:$src), "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", [(set GR8:$dst, (trunc GR32:$src))]>, Requires<[In64BitMode]>; -def TRUNC_16to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16:$src), +def TRUNC_16to8 : I<0x88, MRMDestReg, (outs GR8:$dst), (ins GR16:$src), "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", [(set GR8:$dst, (trunc GR16:$src))]>, Requires<[In64BitMode]>; -def TRUNC_64to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR64:$src), +def TRUNC_64to16 : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR64:$src), "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}", [(set GR16:$dst, (trunc GR64:$src))]>; -def TRUNC_64to32 : I<0x89, MRMDestReg, (ops GR32:$dst, GR64:$src), +def TRUNC_64to32 : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR64:$src), "mov{l} {${src:subreg32}, $dst|$dst, ${src:subreg32}}", [(set GR32:$dst, (trunc GR64:$src))]>; // Zero-extension // TODO: Remove this after proper i32 -> i64 zext support. -def PsMOVZX64rr32: I<0x89, MRMDestReg, (ops GR64:$dst, GR32:$src), +def PsMOVZX64rr32: I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src), "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}", [(set GR64:$dst, (zext GR32:$src))]>; -def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (ops GR64:$dst, i32mem:$src), +def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>; @@ -1010,13 +1016,13 @@ def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (ops GR64:$dst, i32mem:$src), // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove // when we have a better way to specify isel priority. let AddedComplexity = 1 in -def MOV64r0 : RI<0x31, MRMInitReg, (ops GR64:$dst), +def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins), "xor{q} $dst, $dst", [(set GR64:$dst, 0)]>; // Materialize i64 constant where top 32-bits are zero. let AddedComplexity = 1 in -def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (ops GR64:$dst, i64i32imm:$src), +def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}", [(set GR64:$dst, i64immZExt32:$src)]>; @@ -1132,34 +1138,34 @@ def : Pat<(subc GR64:$src1, i64immSExt8:$src2), // Move instructions... -def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR64:$src), +def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector GR64:$src)))]>; -def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>; -def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, VR128:$src), +def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (vector_extract (v2i64 VR128:$src), (iPTR 0)))]>; -def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, VR128:$src), +def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(store (i64 (vector_extract (v2i64 VR128:$src), (iPTR 0))), addr:$dst)]>; -def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (ops FR64:$dst, GR64:$src), +def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(set FR64:$dst, (bitconvert GR64:$src))]>; -def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (ops FR64:$dst, i64mem:$src), +def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>; -def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, FR64:$src), +def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (bitconvert FR64:$src))]>; -def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, FR64:$src), +def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), "mov{d|q} {$src, $dst|$dst, $src}", [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index dd6cf36f7d..f4fd4522ae 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -936,8 +936,8 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, } -const unsigned *X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) - const { +const unsigned * +X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { static const unsigned CalleeSavedRegs32Bit[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 }; diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 0ec9a063a0..cdec55f329 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -87,8 +87,8 @@ public: /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred /// register classes to spill each callee-saved register with. The order and /// length of this list match the getCalleeSavedRegs() list. - const TargetRegisterClass* const* getCalleeSavedRegClasses( - const MachineFunction *MF = 0) const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; /// getReservedRegs - Returns a bitset indexed by physical register number /// indicating if a register is a special register that has particular uses and diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 3f59c23a87..99da8d6e49 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -76,6 +76,10 @@ namespace llvm { MINumOperands(MINO), MIOperandInfo(MIOI) {} }; + /// NumDefs - Number of def operands declared. + /// + unsigned NumDefs; + /// OperandList - The list of declared operands, along with their declared /// type (which is a record). std::vector<OperandInfo> OperandList; diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index 2aabe51c51..268711da53 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -376,13 +376,25 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) DagInit *DI; try { - DI = R->getValueAsDag("OperandList"); + DI = R->getValueAsDag("OutOperandList"); } catch (...) { // Error getting operand list, just ignore it (sparcv9). AsmString.clear(); OperandList.clear(); return; } + NumDefs = DI->getNumArgs(); + + DagInit *IDI; + try { + IDI = R->getValueAsDag("InOperandList"); + } catch (...) { + // Error getting operand list, just ignore it (sparcv9). + AsmString.clear(); + OperandList.clear(); + return; + } + DI = (DagInit*)(new BinOpInit(BinOpInit::CONCAT, DI, IDI))->Fold(); unsigned MIOperandNo = 0; std::set<std::string> OperandNames; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index fcad318587..e8049d6baf 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -1171,7 +1171,12 @@ void DAGISelEmitter::ParsePatternFragments(std::ostream &OS) { // Parse the operands list. DagInit *OpsList = Fragments[i]->getValueAsDag("Operands"); DefInit *OpsOp = dynamic_cast<DefInit*>(OpsList->getOperator()); - if (!OpsOp || OpsOp->getDef()->getName() != "ops") + // Special cases: ops == outs == ins. Different names are used to + // improve readibility. + if (!OpsOp || + (OpsOp->getDef()->getName() != "ops" && + OpsOp->getDef()->getName() != "outs" && + OpsOp->getDef()->getName() != "ins")) P->error("Operands list should start with '(ops ... '!"); // Copy over the arguments. diff --git a/utils/TableGen/Record.cpp b/utils/TableGen/Record.cpp index e81a361eae..75583bb1d1 100644 --- a/utils/TableGen/Record.cpp +++ b/utils/TableGen/Record.cpp @@ -396,8 +396,18 @@ Init *BinOpInit::Fold() { if (LHSs && RHSs) { DefInit *LOp = dynamic_cast<DefInit*>(LHSs->getOperator()); DefInit *ROp = dynamic_cast<DefInit*>(RHSs->getOperator()); - if (LOp->getDef() != ROp->getDef()) - throw "Concated Dag operators do not match!"; + if (LOp->getDef() != ROp->getDef()) { + bool LIsOps = + LOp->getDef()->getName() == "outs" || + LOp->getDef()->getName() != "ins" || + LOp->getDef()->getName() != "defs"; + bool RIsOps = + ROp->getDef()->getName() == "outs" || + ROp->getDef()->getName() != "ins" || + ROp->getDef()->getName() != "defs"; + if (!LIsOps || !RIsOps) + throw "Concated Dag operators do not match!"; + } std::vector<Init*> Args; std::vector<std::string> ArgNames; for (unsigned i = 0, e = LHSs->getNumArgs(); i != e; ++i) { |