Match tablegen changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 118 insertions, 129 deletions

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 8d2cbfd5bb..7673c978b5 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -317,7 +317,7 @@ public:
     : SelectionDAGISel(Lowering), Lowering(TM) {
   }
 
-  void Select(SDOperand &Result, SDOperand Op);
+  SDNode *Select(SDOperand &Result, SDOperand Op);
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
   bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
 
@@ -346,14 +346,15 @@ bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
   return true;      //any address fits in a register
 }
 
-void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   SDNode *N = Op.Val;
 
   switch (N->getOpcode()) {
   default:
-    SelectCode(Result, Op);
+    return SelectCode(Result, Op);
     break;
   }
+  return NULL;
 }
 
 }  // end anonymous namespace
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 811aab85d0..8cc95ab804 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -110,7 +110,7 @@ namespace {
 
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    void Select(SDOperand &Result, SDOperand Op);
+    SDNode *Select(SDOperand &Result, SDOperand Op);
     
     /// InstructionSelectBasicBlock - This callback is invoked by
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@@ -181,35 +181,35 @@ void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
       N->getOpcode() < AlphaISD::FIRST_NUMBER) {
     Result = Op;
-    return;   // Already selected.
+    return NULL;   // Already selected.
   }
 
   switch (N->getOpcode()) {
   default: break;
   case AlphaISD::CALL:
     Result = SelectCALL(Op);
-    return;
+    return NULL;
 
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
                                   CurDAG->getTargetFrameIndex(FI, MVT::i32),
                                   getI64Imm(0));
-    return;
+    return NULL;
   }
   case AlphaISD::GlobalBaseReg: 
     Result = getGlobalBaseReg();
     ReplaceUses(Op, Result);
-    return;
+    return NULL;
   case AlphaISD::GlobalRetAddr:
     Result = getGlobalRetAddr();
     ReplaceUses(Op, Result);
-    return;
+    return NULL;
   
   case AlphaISD::DivCall: {
     SDOperand Chain = CurDAG->getEntryNode();
@@ -229,7 +229,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, 
 				  SDOperand(CNode, 1));
     Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
-    return;
+    return NULL;
   }
 
   case ISD::READCYCLECOUNTER: {
@@ -237,9 +237,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     AddToQueue(Chain, N->getOperand(0)); //Select chain
     Result = SDOperand(CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
                                              Chain), Op.ResNo);
-    ReplaceUses(Op.getValue(0), Result.getValue(0));
-    ReplaceUses(Op.getValue(1), Result.getValue(1));
-    return;
+    return Result.Val;
   }
 
   case ISD::Constant: {
@@ -249,7 +247,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
                                       MVT::i64);
       ReplaceUses(Op, Result);
-      return;
+      return NULL;
     }
 
     int64_t val = (int64_t)uval;
@@ -270,7 +268,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                         getGlobalBaseReg());
     Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, 
                                   CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
-    return;
+    return NULL;
   }
   case ISD::TargetConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
@@ -280,12 +278,12 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
                                     T, CurDAG->getRegister(Alpha::F31, T),
                                     CurDAG->getRegister(Alpha::F31, T));
-      return;
+      return NULL;
     } else if ( CN->isExactlyValue(-0.0)) {
       Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
                                     T, CurDAG->getRegister(Alpha::F31, T),
                                     CurDAG->getRegister(Alpha::F31, T));
-      return;
+      return NULL;
     } else {
       abort();
     }
@@ -335,8 +333,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, 
                                                CurDAG->getRegister(Alpha::R31, MVT::i64),
                                                LD), 0);
-      ReplaceUses(Op, Result);
-      return;
+      return Result.Val;
     }
     break;
 
@@ -369,8 +366,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       }
       Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
                                                MVT::f64, FV, TV, LD), 0);
-      ReplaceUses(Op, Result);
-      return;
+      return Result.Val;
     }
     break;
 
@@ -401,8 +397,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 					    getI64Imm(get_zapImm(mask))), 0);
 	  Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z, 
 						   getI64Imm(sval)), 0);
-          ReplaceUses(Op, Result);
-	  return;
+	  return Result.Val;
 	}
       }
     break;
@@ -410,7 +405,7 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 
   }
 
-  SelectCode(Result, Op);
+  return SelectCode(Result, Op);
 }
 
 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 8013f87589..20a6fd6a44 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -65,7 +65,7 @@ namespace {
     
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    void Select(SDOperand &Result, SDOperand N);
+    SDNode *Select(SDOperand &Result, SDOperand N);
     
     SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
                                    unsigned OCHi, unsigned OCLo,
@@ -296,12 +296,12 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
       N->getOpcode() < IA64ISD::FIRST_NUMBER) {
     Result = Op;
-    return;   // Already selected.
+    return NULL;   // Already selected.
   }
 
   switch (N->getOpcode()) {
@@ -376,15 +376,14 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
      ReplaceUses(Op.getValue(i), CallResults[i]);
    Result = CallResults[Op.ResNo];
-   return;
+   return NULL;
   }
   
   case IA64ISD::GETFD: {
     SDOperand Input;
     AddToQueue(Input, N->getOperand(0));
     Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
   } 
   
   case ISD::FDIV:
@@ -393,8 +392,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   case ISD::SREM:
   case ISD::UREM:
     Result = SelectDIV(Op);
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
  
   case ISD::TargetConstantFP: {
     SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
@@ -405,20 +403,20 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
     } else
       assert(0 && "Unexpected FP constant!");
-    return;
+    return Result.Val;
   }
 
   case ISD::FrameIndex: { // TODO: reduce creepyness
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    if (N->hasOneUse())
+    if (N->hasOneUse()) {
       Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
                                   CurDAG->getTargetFrameIndex(FI, MVT::i64));
-    else {
+      return NULL;
+    } else {
       Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
                                 CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
-      ReplaceUses(Op, Result);
+      return Result.Val;
     }
-    return;
   }
 
   case ISD::ConstantPool: { // TODO: nuke the constant pool
@@ -429,8 +427,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                                   CP->getAlignment());
     Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
 	                      CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
   }
 
   case ISD::GlobalAddress: {
@@ -439,8 +436,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, 
 	                          CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
     Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
   }
   
 /* XXX  case ISD::ExternalSymbol: {
@@ -475,7 +471,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                     SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
                                   CurDAG->getRegister(IA64::r0, MVT::i64), 
                                   Chain).getValue(Op.ResNo);
-        return;
+        return NULL;
       }
       /* otherwise, we want to load a bool into something bigger: LD1
          will do that for us, so we just fall through */
@@ -492,7 +488,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     // TODO: comment this
     Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
                                 Address, Chain).getValue(Op.ResNo);
-    return;
+    return NULL;
   }
   
   case ISD::TRUNCSTORE:
@@ -517,7 +513,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                               CurDAG->getConstant(1, MVT::i64),
                                               Tmp), 0);
         Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
-        return;
+        return NULL;
       }
       case MVT::i64: Opc = IA64::ST8;  break;
       case MVT::f64: Opc = IA64::STF8; break;
@@ -536,7 +532,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     AddToQueue(N1, N->getOperand(1));
     AddToQueue(N2, N->getOperand(2));
     Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
-    return;
+    return NULL;
   }
 
   case ISD::BRCOND: {
@@ -548,7 +544,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     //FIXME - we do NOT need long branches all the time
     Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, 
                                 CurDAG->getBasicBlock(Dest), Chain);
-    return;
+    return NULL;
   }
 
   case ISD::CALLSEQ_START:
@@ -559,7 +555,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     SDOperand N0;
     AddToQueue(N0, N->getOperand(0));
     Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
-    return;
+    return NULL;
   }
 
   case ISD::BR:
@@ -568,10 +564,10 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     AddToQueue(N0, N->getOperand(0));
     Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, 
                                 N->getOperand(1), N0);
-    return;
+    return NULL;
   }
   
-  SelectCode(Result, Op);
+  return SelectCode(Result, Op);
 }
 
 
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 106243a68f..91482f712c 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -83,7 +83,7 @@ namespace {
     
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    void Select(SDOperand &Result, SDOperand Op);
+    SDNode *Select(SDOperand &Result, SDOperand Op);
     
     SDNode *SelectBitfieldInsert(SDNode *N);
 
@@ -166,8 +166,8 @@ namespace {
     
 private:
     SDOperand SelectSETCC(SDOperand Op);
-    void MySelect_PPCbctrl(SDOperand &Result, SDOperand N);
-    void MySelect_PPCcall(SDOperand &Result, SDOperand N);
+    SDNode *MySelect_PPCbctrl(SDOperand &Result, SDOperand N);
+    SDNode *MySelect_PPCcall(SDOperand &Result, SDOperand N);
   };
 }
 
@@ -900,23 +900,22 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
       N->getOpcode() < PPCISD::FIRST_NUMBER) {
     Result = Op;
-    return;   // Already selected.
+    return NULL;   // Already selected.
   }
 
   switch (N->getOpcode()) {
   default: break;
   case ISD::SETCC:
     Result = SelectSETCC(Op);
-    return;
+    return NULL;
   case PPCISD::GlobalBaseReg:
     Result = getGlobalBaseReg();
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
     
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
@@ -925,13 +924,12 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     if (N->hasOneUse()) {
       Result = CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
                                     getSmallIPtrImm(0));
-      return;
+      return NULL;
     }
     Result =
       SDOperand(CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
                                       getSmallIPtrImm(0)), 0);
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
   }
 
   case PPCISD::MFCR: {
@@ -943,8 +941,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                                N->getOperand(0), InFlag), 0);
     else
       Result = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag), 0);
-    ReplaceUses(Op, Result);
-    return;
+    return Result.Val;
   }
     
   case ISD::SDIV: {
@@ -973,7 +970,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                     0);
         Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
       }
-      return;
+      return NULL;
     }
     
     // Other cases are autogenerated.
@@ -992,7 +989,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       } else if (Imm == 0) {
         // AND X, 0 -> 0, not "rlwinm 32".
         AddToQueue(Result, N->getOperand(1));
-        return ;
+        return NULL;
       } else {        
         AddToQueue(Val, N->getOperand(0));
         isRunOfOnes(Imm, MB, ME);
@@ -1001,7 +998,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
                                     getI32Imm(SH), getI32Imm(MB),
                                     getI32Imm(ME));
-      return;
+      return NULL;
     }
     // ISD::OR doesn't get all the bitfield insertion fun.
     // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
@@ -1018,8 +1015,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                                  Tmp1, Tmp2,
                                                  getI32Imm(0), getI32Imm(MB),
                                                  getI32Imm(ME)), 0);
-        ReplaceUses(Op, Result);
-        return;
+        return Result.Val;
       }
     }
     
@@ -1030,8 +1026,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     if (N->getValueType(0) == MVT::i32)
       if (SDNode *I = SelectBitfieldInsert(N)) {
         Result = SDOperand(I, 0);
-        ReplaceUses(Op, Result);
-        return;
+        return Result.Val;
       }
       
     // Other cases are autogenerated.
@@ -1045,7 +1040,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
                                     Val, getI32Imm(SH), getI32Imm(MB),
                                     getI32Imm(ME));
-      return;
+      return NULL;
     }
     
     // Other cases are autogenerated.
@@ -1060,7 +1055,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
       Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
                                     Val, getI32Imm(SH), getI32Imm(MB),
                                     getI32Imm(ME));
-      return;
+      return NULL;
     }
     
     // Other cases are autogenerated.
@@ -1085,7 +1080,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
             Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
                                           SDOperand(Tmp, 0), LHS,
                                           SDOperand(Tmp, 1));
-            return;
+            return NULL;
           }
 
     SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
@@ -1109,7 +1104,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     AddToQueue(N3, N->getOperand(3));
     Result = CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
                                   N2, N3, getI32Imm(BROpc));
-    return;
+    return NULL;
   }
   case ISD::BR_CC: {
     SDOperand Chain;
@@ -1119,7 +1114,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, 
                                   CondCode, getI32Imm(getBCCForSetCC(CC)), 
                                   N->getOperand(4), Chain);
-    return;
+    return NULL;
   }
   case ISD::BRIND: {
     // FIXME: Should custom lower this.
@@ -1130,23 +1125,22 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
                                             Chain), 0);
     Result = CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
-    return;
+    return NULL;
   }
   // FIXME: These are manually selected because tblgen isn't handling varargs
   // nodes correctly.
-  case PPCISD::BCTRL:            MySelect_PPCbctrl(Result, Op); return;
-  case PPCISD::CALL:             MySelect_PPCcall(Result, Op); return;
+  case PPCISD::BCTRL:            return MySelect_PPCbctrl(Result, Op);
+  case PPCISD::CALL:             return MySelect_PPCcall(Result, Op);
   }
   
-  SelectCode(Result, Op);
+  return SelectCode(Result, Op);
 }
 
 
 // FIXME: This is manually selected because tblgen isn't handling varargs nodes
 // correctly.
-void PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand &Result, SDOperand N) {
+SDNode *PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand &Result, SDOperand N) {
   SDOperand Chain(0, 0);
-  SDOperand InFlag(0, 0);
   SDNode *ResNode;
   
   bool hasFlag =
@@ -1169,19 +1163,14 @@ void PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand &Result, SDOperand N) {
   
   ResNode = CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag,
                                   &Ops[0], Ops.size());
-  Chain = SDOperand(ResNode, 0);
-  InFlag = SDOperand(ResNode, 1);
-  ReplaceUses(SDOperand(N.Val, 0), Chain);
-  ReplaceUses(SDOperand(N.Val, 1), InFlag);
   Result = SDOperand(ResNode, N.ResNo);
-  return;
+  return ResNode;
 }
 
 // FIXME: This is manually selected because tblgen isn't handling varargs nodes
 // correctly.
-void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
+SDNode *PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
   SDOperand Chain(0, 0);
-  SDOperand InFlag(0, 0);
   SDOperand N1(0, 0);
   SDOperand Tmp0(0, 0);
   SDNode *ResNode;
@@ -1214,12 +1203,8 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
     ResNode = CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
                                     &Ops[0], Ops.size());
     
-    Chain = SDOperand(ResNode, 0);
-    InFlag = SDOperand(ResNode, 1);
-    ReplaceUses(SDOperand(N.Val, 0), Chain);
-    ReplaceUses(SDOperand(N.Val, 1), InFlag);
     Result = SDOperand(ResNode, N.ResNo);
-    return;
+    return ResNode;
   }
   
   // Pattern: (PPCcall:void (tglobaladdr:i32):$dst)
@@ -1247,12 +1232,8 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
     ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
                                     &Ops[0], Ops.size());
     
-    Chain = SDOperand(ResNode, 0);
-    InFlag = SDOperand(ResNode, 1);
-    ReplaceUses(SDOperand(N.Val, 0), Chain);
-    ReplaceUses(SDOperand(N.Val, 1), InFlag);
     Result = SDOperand(ResNode, N.ResNo);
-    return;
+    return ResNode;
   }
   
   // Pattern: (PPCcall:void (texternalsym:i32):$dst)
@@ -1280,17 +1261,15 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
     ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
                                     &Ops[0], Ops.size());
 
-    Chain = SDOperand(ResNode, 0);
-    InFlag = SDOperand(ResNode, 1);
-    ReplaceUses(SDOperand(N.Val, 0), Chain);
-    ReplaceUses(SDOperand(N.Val, 1), InFlag);
     Result = SDOperand(ResNode, N.ResNo);
-    return;
+    return ResNode;
   }
   std::cerr << "Cannot yet select: ";
   N.Val->dump(CurDAG);
   std::cerr << '\n';
   abort();
+
+  return NULL;
 }
 
 
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 765982dd2d..6a94ac2f8e 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -966,7 +966,7 @@ public:
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }
 
-  void Select(SDOperand &Result, SDOperand Op);
+  SDNode *Select(SDOperand &Result, SDOperand Op);
 
   // Complex Pattern Selectors.
   bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
@@ -1063,12 +1063,12 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
   return true;
 }
 
-void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
       N->getOpcode() < SPISD::FIRST_NUMBER) {
     Result = Op;
-    return;   // Already selected.
+    return NULL;   // Already selected.
   }
 
   switch (N->getOpcode()) {
@@ -1094,7 +1094,7 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     // FIXME: Handle div by immediate.
     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
     Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
-    return;
+    return NULL;
   }    
   case ISD::MULHU:
   case ISD::MULHS: {
@@ -1107,11 +1107,11 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                         MulLHS, MulRHS);
     // The high part is in the Y register.
     Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
-    return;
+    return NULL;
   }
   }
   
-  SelectCode(Result, Op);
+  return SelectCode(Result, Op);
 }
 
 
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 1cfc9af9d9..a5983479a6 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -123,7 +123,7 @@ namespace {
 #include "X86GenDAGISel.inc"
 
   private:
-    void Select(SDOperand &Result, SDOperand N);
+    SDNode *Select(SDOperand &Result, SDOperand N);
 
     bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
     bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
@@ -646,7 +646,7 @@ static SDNode *FindCallStartFromCall(SDNode *Node) {
   return FindCallStartFromCall(Node->getOperand(0).Val);
 }
 
-void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
+SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
   SDNode *Node = N.Val;
   MVT::ValueType NVT = Node->getValueType(0);
   unsigned Opc, MOpc;
@@ -669,15 +669,14 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
     DEBUG(std::cerr << "\n");
     Indent -= 2;
 #endif
-    return;   // Already selected.
+    return NULL;   // Already selected.
   }
 
   switch (Opcode) {
     default: break;
     case X86ISD::GlobalBaseReg: 
       Result = getGlobalBaseReg();
-      ReplaceUses(N, Result);
-      return;
+      return Result.Val;
 
     case ISD::ADD: {
       // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
@@ -705,12 +704,12 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         if (C.Val) {
           if (N.Val->hasOneUse()) {
             Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
+	    return NULL;
           } else {
             SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
             Result = SDOperand(ResNode, 0);
-            ReplaceUses(N, Result);
+	    return ResNode;
           }
-          return;
         }
       }
 
@@ -798,7 +797,7 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
       DEBUG(std::cerr << "\n");
       Indent -= 2;
 #endif
-      return;
+      return NULL;
     }
       
     case ISD::SDIV:
@@ -902,7 +901,8 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
       DEBUG(std::cerr << "\n");
       Indent -= 2;
 #endif
-      return;
+
+      return NULL;
     }
 
     case ISD::TRUNCATE: {
@@ -927,7 +927,6 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         AddToQueue(Tmp0, Node->getOperand(0));
         Tmp1 = SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0);
         Result = SDOperand(CurDAG->getTargetNode(Opc2, NVT, Tmp1), 0);
-        ReplaceUses(N, Result);
       
 #ifndef NDEBUG
         DEBUG(std::cerr << std::string(Indent-2, ' '));
@@ -936,14 +935,15 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         DEBUG(std::cerr << "\n");
         Indent -= 2;
 #endif
-        return;
+        return Result.Val;
       }
 
       break;
     }
   }
 
-  SelectCode(Result, N);
+  SDNode *ResNode = SelectCode(Result, N);
+
 #ifndef NDEBUG
   DEBUG(std::cerr << std::string(Indent-2, ' '));
   DEBUG(std::cerr << "=> ");
@@ -951,6 +951,8 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
   DEBUG(std::cerr << "\n");
   Indent -= 2;
 #endif
+
+  return ResNode;
 }
 
 bool X86DAGToDAGISel::
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 4b07470022..69b3dea030 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2992,9 +2992,14 @@ SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
   }
   Constant *CS = ConstantStruct::get(CV);
   SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
-  SDOperand Mask 
-    = DAG.getNode(X86ISD::LOAD_PACK,
-                  VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+  std::vector<MVT::ValueType> Tys;
+  Tys.push_back(VT);
+  Tys.push_back(MVT::Other);
+  SmallVector<SDOperand, 3> Ops;
+  Ops.push_back(DAG.getEntryNode());
+  Ops.push_back(CPIdx);
+  Ops.push_back(DAG.getSrcValue(NULL));
+  SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
   return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
 }
 
@@ -3013,8 +3018,14 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
   }
   Constant *CS = ConstantStruct::get(CV);
   SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
-  SDOperand Mask  = DAG.getNode(X86ISD::LOAD_PACK,
-                          VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+  std::vector<MVT::ValueType> Tys;
+  Tys.push_back(VT);
+  Tys.push_back(MVT::Other);
+  SmallVector<SDOperand, 3> Ops;
+  Ops.push_back(DAG.getEntryNode());
+  Ops.push_back(CPIdx);
+  Ops.push_back(DAG.getSrcValue(NULL));
+  SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
   return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
 }
 
@@ -4121,10 +4132,15 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
                        Base->getOperand(2));
   else {
     // Just use movups, it's shorter.
+    std::vector<MVT::ValueType> Tys;
+    Tys.push_back(MVT::v4f32);
+    Tys.push_back(MVT::Other);
+    SmallVector<SDOperand, 3> Ops;
+    Ops.push_back(Base->getOperand(0));
+    Ops.push_back(Base->getOperand(1));
+    Ops.push_back(Base->getOperand(2));
     return DAG.getNode(ISD::BIT_CONVERT, VT,
-                       DAG.getNode(X86ISD::LOAD_UA, MVT::v4f32,
-                                   Base->getOperand(0), Base->getOperand(1),
-                                   Base->getOperand(2)));
+                       DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
   }
 }