diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2013-01-10 23:22:53 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2013-01-10 23:22:53 +0000 |
| commit | 582e4f278b95d50a45c6f56e33da5e78c19afc17 (patch) | |
| tree | 40554ee8f36be2e6a9d9982303424bcf10e2d4e0 | |
| parent | 0e4776ce61092e34ac2340c60534cbed29aba87b (diff) | |
CastInst::castIsValid should return true if the dest type is the same as
Value's current type. The casting is trivial even for aggregate type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172143 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/IR/Instructions.cpp | 5 | ||||
| -rw-r--r-- | test/Transforms/MergeFunc/2013-01-10-MergeFuncAssert.ll | 36 |
2 files changed, 41 insertions, 0 deletions
diff --git a/lib/IR/Instructions.cpp b/lib/IR/Instructions.cpp index f2e9813bc6..26398ce851 100644 --- a/lib/IR/Instructions.cpp +++ b/lib/IR/Instructions.cpp @@ -2624,6 +2624,11 @@ CastInst::castIsValid(Instruction::CastOps op, Value *S, Type *DstTy) { // Check for type sanity on the arguments Type *SrcTy = S->getType(); + + // If this is a cast to the same type then it's trivially true. + if (SrcTy == DstTy) + return true; + if (!SrcTy->isFirstClassType() || !DstTy->isFirstClassType() || SrcTy->isAggregateType() || DstTy->isAggregateType()) return false; diff --git a/test/Transforms/MergeFunc/2013-01-10-MergeFuncAssert.ll b/test/Transforms/MergeFunc/2013-01-10-MergeFuncAssert.ll new file mode 100644 index 0000000000..3f6a5ba157 --- /dev/null +++ b/test/Transforms/MergeFunc/2013-01-10-MergeFuncAssert.ll @@ -0,0 +1,36 @@ +; RUN: opt -mergefunc -disable-output < %s +; This used to trigger a ConstantExpr::getBitCast assertion. + +define void @t1() unnamed_addr uwtable ssp align 2 { +entry: + switch i32 undef, label %sw.bb12 [ + i32 127, label %sw.bb + i32 126, label %sw.bb4 + ] + +sw.bb: ; preds = %entry + unreachable + +sw.bb4: ; preds = %entry + unreachable + +sw.bb12: ; preds = %entry + ret void +} + +define void @t2() unnamed_addr uwtable ssp align 2 { +entry: + switch i32 undef, label %sw.bb8 [ + i32 4, label %sw.bb + i32 3, label %sw.bb4 + ] + +sw.bb: ; preds = %entry + unreachable + +sw.bb4: ; preds = %entry + ret void + +sw.bb8: ; preds = %entry + unreachable +} |