aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDevang Patel <dpatel@apple.com>2012-01-10 17:51:54 +0000
committerDevang Patel <dpatel@apple.com>2012-01-10 17:51:54 +0000
commit4ba0e75e4b1c557a9de5a3675357c2a4bf699a6a (patch)
tree9745baba0f24058607834a99fb86cdddf5395890
parent56315d319c104dc96187444e1e19711a1c801166 (diff)
Add definition for intel asm variant.
Right now, this just adds additional entries in match table. The parser does not use them yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147859 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86.td12
1 files changed, 11 insertions, 1 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index c76d4e51db..3b2d27c746 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -263,6 +263,16 @@ def ATTAsmParserVariant : AsmParserVariant {
string RegisterPrefix = "%";
}
+def IntelAsmParserVariant : AsmParserVariant {
+ int Variant = 1;
+
+ // Discard comments in assembly strings.
+ string CommentDelimiter = ";";
+
+ // Recognize hard coded registers.
+ string RegisterPrefix = "";
+}
+
//===----------------------------------------------------------------------===//
// Assembly Printers
//===----------------------------------------------------------------------===//
@@ -284,6 +294,6 @@ def X86 : Target {
// Information about the instructions...
let InstructionSet = X86InstrInfo;
let AssemblyParsers = [ATTAsmParser];
- let AssemblyParserVariants = [ATTAsmParserVariant];
+ let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
}