Prepare for adding InstrSchedModel annotations to X86 instructions.

The new InstrSchedModel is easier to use than the instruction
itineraries. It will be used to model instruction latency and throughput
in modern Intel microarchitectures like Sandy Bridge.

InstrSchedModel should be able to coexist with instruction itinerary
classes, but for cleanliness we should switch the Atom processor model
to the new InstrSchedModel as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 0 deletions

diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td
index d99d085298..5c57520fd0 100644
--- a/lib/Target/X86/X86Schedule.td
+++ b/lib/Target/X86/X86Schedule.td
@@ -7,6 +7,32 @@
 //
 //===----------------------------------------------------------------------===//
 
+// InstrSchedModel annotations for out-of-order CPUs.
+//
+// These annotations are independent of the itinerary classes defined below.
+
+// Instructions with folded loads need to read the memory operand immediately,
+// but other register operands don't have to be read until the load is ready.
+// These are marked with ReadAfterLd.
+def ReadAfterLd : SchedRead;
+
+// Instructions with both a load and a store folded are modeled as a folded
+// load + WriteRMW.
+def WriteRMW : SchedWrite;
+
+// Most instructions can fold loads, so every SchedWrite comes in two variants:
+// With and without a folded load.
+
+// Arithmetic.
+def WriteALU     : SchedWrite; // Simple integer ALU op.
+def WriteALULd   : SchedWrite; // ALU op with folded load.
+def WriteIMul    : SchedWrite; // Integer multiplication.
+def WriteIMulLd  : SchedWrite;
+def WriteIDiv    : SchedWrite; // Integer division.
+def WriteIDivLd  : SchedWrite;
+def WriteLEA     : SchedWrite; // LEA instructions can't fold loads.
+
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for X86
 def IIC_DEFAULT     : InstrItinClass;