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| author | Logan Chien <tzuhsiang.chien@gmail.com> | 2013-04-16 14:02:30 +0000 |
|---|---|---|
| committer | Logan Chien <tzuhsiang.chien@gmail.com> | 2013-04-16 14:02:30 +0000 |
| commit | a363b117f41700da0200753e6df62b5e2cb38378 (patch) | |
| tree | 801b0286ab4d0caab2f90bfe4972db54bf203c88 | |
| parent | 532854d7ab47d4ec20fd8cec703aa8c89d4eefb2 (diff) | |
Fix build failure introduced in 179591 when assertions are disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179593 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index f17dcdf6ab..52d92375aa 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -428,7 +428,9 @@ void ARMELFStreamer::EmitSetFP(unsigned NewFPReg, const MCRegisterInfo &MRI = getContext().getRegisterInfo(); uint16_t NewFPRegEncVal = MRI.getEncodingValue(NewFPReg); +#ifndef NDEBUG uint16_t NewSPRegEncVal = MRI.getEncodingValue(NewSPReg); +#endif assert((NewSPReg == ARM::SP || NewSPRegEncVal == FPReg) && "the operand of .setfp directive should be either $sp or $fp"); @@ -446,7 +448,9 @@ void ARMELFStreamer::EmitRegSave(const SmallVectorImpl<unsigned> &RegList, bool IsVector) { const MCRegisterInfo &MRI = getContext().getRegisterInfo(); +#ifndef NDEBUG unsigned Max = IsVector ? 32 : 16; +#endif uint32_t &RegMask = IsVector ? VFPRegSave : RegSave; for (size_t i = 0; i < RegList.size(); ++i) { |